Re: [PATCH 1/2] dt-bindings: pinctrl: qcom: Describe Maili TLMM block

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The example's `gpio-ranges` specifies a count of 227, contradicting the hardware's actual pin count of 226.
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commit 8e1650eabb9fd79edf142e0abd0dc0d09fa8eeb4
Author: Jingyi Wang <jingyi.wang@oss.qualcomm.com>

dt-bindings: pinctrl: qcom: Describe Maili TLMM block

This commit adds a DeviceTree binding to describe the Top Level Mode
Multiplexer (TLMM) on Qualcomm's Maili SoC. The block provides GPIO and
pinctrl functionality for UFS, SDC and 226 GPIO pins.

> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml
> new file mode 100644
> index 0000000000000..64fe90b2391bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    tlmm: pinctrl@f100000 {
> +        compatible = "qcom,maili-tlmm";
> +        reg = <0x0f100000 0x300000>;
> +        interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
> +        gpio-controller;
> +        #gpio-cells = <2>;
> +        gpio-ranges = <&tlmm 0 0 227>;

[Severity: Low]
The commit message mentions the hardware provides 226 GPIO pins, and the
schema enforces this limit in gpio-line-names and the pins pattern. Should
this example's gpio-ranges specify a count of 226 instead of 227 to avoid
contradicting the hardware pin count?

> +        interrupt-controller;
> +        #interrupt-cells = <2>;

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260522-maili-pinctrl-v1-0-0a6636f5c277@oss.qualcomm.com?part=1