From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 398DD3B2FF8; Fri, 22 May 2026 10:23:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445395; cv=none; b=BSZimyBXgdM7o4l7WcAO6Yt4i8ntTKsi9MFMMEa8UFaIf4ZYprjHaXxFSxKKvc2NVrY5yYqHqKKxDRPsIWgxiXRiKSOCL8fpDgntPaIHOpSKdl9Hd0wjEysanJdLWxQuwfj4htUJj3t2pC8vpxlpNReH23B1hriW1wHLk50odFU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779445395; c=relaxed/simple; bh=DXD7PWBDcpnRwnx3My/g2cSTbxWvZsLQNb1TLHUZU0U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hpnITV5SuKy6Hae5zOGwDEllnCKb6nqDqgR2x7sFbiIqtuU0tOHeJonFUrGFNZVyx70fSBGHDRkIBse5kd8Lq27n6pW7x30z6GuHX+T5byKBgHfW1dj0yndvkf0vzEbaTiR/TegKKsBMe2gVhKVoml57mZ8gu89418EEOcjiK+k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e6SDvqlW; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e6SDvqlW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D4A91F000E9; Fri, 22 May 2026 10:23:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779445388; bh=pHdLavqRXkA3FHH3+USq+datVIb7v/EfPh2zTHQx5FI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=e6SDvqlWS20S990IcKWSwkDGeezIULKSZEiw8GgSkby7Q9zx1fK0OjxfZeZLPeUUo RGH0984aKof2gx0VvX9Xgqd+w5WQKICBnfCtTLvV7QJwbisL2WE8YTOTkuCNzVXryK Q11E1p0Pht1+LHAaerhqKMkhHUc6HaqmrtyM1hW4hnX9bZhwE0BqWMK1VhsGEr2i+n Le3u8qaZ7UKJX2332rQDtpXnXs4CY2tizFDYN02MldXRq9t0HES4wZn/bnQXnLs4Ah SHMg8MCMD1LH0WSuO9h+VmY02/sQ/cwP7Fc/JCG0ZGRqY79ilYZ/DLxIFmB5L+Jo43 +g1O9Ul9J3QbA== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, wsa+renesas@sang-engineering.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 2/9] pinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfg Date: Fri, 22 May 2026 13:22:44 +0300 Message-ID: <20260522102251.1723392-3-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260522102251.1723392-1-claudiu.beznea@kernel.org> References: <20260522102251.1723392-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea Drop the QSPI and OTHER_POC register defines, which are SoC specific and accessible through struct rzg2l_hwcfg::{qspi, other_poc}. Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a648d75a2bd2..77443cf1f431 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -180,8 +180,6 @@ #define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ -#define OTHER_POC (0x3028) /* known on RZ/G3L only */ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ @@ -3816,9 +3814,9 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .regs = { .pwpr = 0x3014, .sd_ch = 0x3000, + .qspi = 0x3008, .eth_poc = 0x300c, .oen = 0x3018, - .qspi = QSPI, }, .iolh_groupa_ua = { /* 3v3 power source */ @@ -3835,7 +3833,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg = { .sd_ch = 0x3004, .eth_poc = 0x3010, .oen = 0x3018, - .other_poc = OTHER_POC, + .other_poc = 0x3028, }, .masks = { .other_poc_pvdd1833_oth_awo_poc = BIT(0), -- 2.43.0