Re: [PATCH v7 2/9] reset: eyeq: Add EyeQ7H compatibles

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `valid_mask` values for several new EyeQ7H reset domains are incorrectly calculated based on the total number of items rather than acting as a bitmask of valid hardware offsets, causing valid reset requests to be rejected.
--

commit 8189291a57ece537a6cbcca42424bb22f1515514
Author: Benoît Monin <benoit.monin@bootlin.com>

reset: eyeq: Add EyeQ7H compatibles

This commit adds support for the reset controllers found in the EyeQ7H OLB.
It introduces three new types of reset domains, defines their respective
configurations, and updates the wait timings.

> diff --git a/drivers/reset/reset-eyeq.c b/drivers/reset/reset-eyeq.c
> index 1a38579838970..381237d50f061 100644
> --- a/drivers/reset/reset-eyeq.c
> +++ b/drivers/reset/reset-eyeq.c
> @@ -73,6 +74,40 @@
>   *  9. PMA0	10. PMA1	11. MPC0	12. MPC1
>   * 13. MPC2	14. MPC3	15. PERIPH
>   *
> + * Known resets in EyeQ7H acc domain 0 (type EQR_EYEQ7H_ACRP)
> + *  1. VMP0	2. XVMP1	3. VMP2		4. VMP3
> + *  5. MPC0	6. MPC1		7. PMA0		8. PMA1
> + *
> + * Known resets in EyeQ7H acc domain 1 (type EQR_EYEQ7H_ACC)
> + *  1. NCORE0	 2. NCORE1	3. NCORE0_M	4. NCORE1_M
> + *  5. NCORE_NOC 6. VMP_NOC	7. MPC_NOC	8. PMA_NOC
> + *
> + * Known resets in EyeQ7H ddr (type EQR_EYEQ7H_CFG)
> + *  0. APB	2. DMI		3. DFI		4. PHY_SMS
> + *  5. CTL_SMS
> + *
> + * Known resets in EyeQ7H east (type EQR_EYEQ7H_CFG)
> + *  0. ISP	2. VEU		3. LBIST
> + *
> + * Known resets in EyeQ7H periph (type EQR_EYEQ6H_SARCR)
> + *  0. gpio	1.EXT TIMER	3.UART		4. SPI
> + *  5. I2C0	6. I2C1		7.I2C2		8. I2S

[ ... ]

> @@ -558,6 +681,113 @@ static const struct eqr_match_data eqr_eyeq6h_acc_data = {

[ ... ]

> +static const struct eqr_domain_descriptor eqr_eyeq7h_ddr_domains[] = {
> +	{
> +		.type = EQR_EYEQ7H_CFG,
> +		.valid_mask = 0x1F,

[Severity: High]
Will this valid_mask reject valid reset requests for the CTL_SMS (offset 5)
reset? 

The known resets listed above include APB (0), DMI (2), DFI (3), PHY_SMS (4),
and CTL_SMS (5). Using 0x1F only covers bits 0 through 4, meaning a request
for offset 5 will fail the bitmask check in eqr_of_xlate_internal() and
return -EINVAL.

Should this mask be 0x3D instead?

> +		.offset = 0x008,
> +	},
> +};

[ ... ]

> +static const struct eqr_domain_descriptor eqr_eyeq7h_per_domains[] = {
> +	{
> +		.type = EQR_EYEQ6H_SARCR,
> +		.valid_mask = 0xFF,

[Severity: High]
Is this mask calculated based on the total number of items rather than acting
as a bitmask of valid hardware offsets? 

The known resets for the periph domain include I2S at offset 8, but a mask
of 0xFF only covers bits 0 through 7. This appears to affect several other
new domains as well (like east and xnn), where the valid_mask value seems
to be calculated as (1 << num_resets) - 1 rather than setting the specific
bits that correspond to the valid offsets.

> +		.offset = 0x030,
> +	},
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260522-clk-eyeq7-v7-0-14ad6c2c5213@bootlin.com?part=2