On Sun, May 24, 2026 at 09:13:07PM +0800, Chuanhong Guo wrote:
> Add the device tree binding header and binding doc for
> Siflower SF21A6826/SF21H8898 toplevel clock and reset module.
> 
> CLK_ETH_REF_P is a clock name that exists in the vendor datasheet.
> This clock connects directly to CLK_PCIEPLL_FOUT2 and there's no
> clock gate/mux in between. An alias is created for this clock
> to make available clock names align with the datasheet.
> 
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable