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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NMZqpzAe82YzDrqQ9mjm+5LCFpqyD7Wwc20liDxzvHaDtJKnZgY1xU9qeSOdwugMVwi7aQ3hyHftG7Jldifzd2ulAQfY+h+zWLR9xSIUcwNS4eA+AJzg6ZSY8tVljpsLRAg7RgZTO/T50xqgvDeGpU72SJKmMN5pBYwfIAAY0hBNbL2kGmDG8m1Szhf/eNlZpgvoTSlo0UQlc7rBnM+rNiMpfJ4XWHgPhv0VXc20t+PelVIw8X8AQ6O6ydTjz+omPe3urFioaLHnyIe6Ksj0PDXCsIyr5zQs3VdnPIEKq1R8EaDc/fOHKiGFB1uVnpFW68bVMXtK1Yb6Pw3nWuI2FfIvdaLk1PhDpqlpSj2M9IktlDzebwK4CgIOnOV3hVJaQWT2pQp+gEyrcvir6X3p7kuDPjLuDbKyg4tE+SIrLq3bl4Qgt8sKGCOLQq6YWgmL X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 17:55:55.4018 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c92f709-6edb-4ad4-b7d1-08debc19335a X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA3PR10MB8662 Some SPI controllers support high-speed operating modes that require controller-side configuration before the device can be driven at its rated maximum. In such cases the device has two relevant speeds: a conservative rate for baseline operation and a maximum rate achievable once the controller is fully configured. Extend struct spi_device with a base_speed_hz field. Update of_spi_parse_dt() to populate base_speed_hz from the first element and max_speed_hz from the second when spi-max-frequency carries two values. A single-element property continues to populate only max_speed_hz, preserving existing behaviour. base_speed_hz is zero when not set. Signed-off-by: Santhosh Kumar K --- drivers/spi/spi.c | 17 ++++++++++++++--- include/linux/spi/spi.h | 2 ++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 76e3563c523f..a1050b1a1d4c 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2364,7 +2364,7 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, struct device_node *nc) { u32 value, cs[SPI_DEVICE_CS_CNT_MAX], map[SPI_DEVICE_DATA_LANE_CNT_MAX]; - int rc, idx, max_num_data_lanes; + int rc, idx, max_num_data_lanes, nfreq; /* Mode (clock phase/polarity/etc.) */ if (of_property_read_bool(nc, "spi-cpha")) @@ -2596,9 +2596,20 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, */ spi->cs_index_mask = BIT(0); - /* Device speed */ - if (!of_property_read_u32(nc, "spi-max-frequency", &value)) + /* + * Device speed: a single value sets max_speed_hz; two values set + * base_speed_hz (conservative) and max_speed_hz (maximum after + * controller-side configuration). + */ + nfreq = of_property_count_u32_elems(nc, "spi-max-frequency"); + if (nfreq == 2) { + of_property_read_u32_index(nc, "spi-max-frequency", 0, + &spi->base_speed_hz); + of_property_read_u32_index(nc, "spi-max-frequency", 1, + &spi->max_speed_hz); + } else if (!of_property_read_u32(nc, "spi-max-frequency", &value)) { spi->max_speed_hz = value; + } /* Device CS delays */ of_spi_parse_dt_cs_delay(nc, &spi->cs_setup, "spi-cs-setup-delay-ns"); diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index f6ed93eff00b..e4fc8ac1c889 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -139,6 +139,7 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, * @max_speed_hz: Maximum clock rate to be used with this chip * (on this board); may be changed by the device's driver. * The spi_transfer.speed_hz can override this for each transfer. + * @base_speed_hz: Conservative clock rate for the device; zero when not set. * @bits_per_word: Data transfers involve one or more words; word sizes * like eight or 12 bits are common. In-memory wordsizes are * powers of two bytes (e.g. 20 bit samples use 32 bits). @@ -191,6 +192,7 @@ struct spi_device { struct device dev; struct spi_controller *controller; u32 max_speed_hz; + u32 base_speed_hz; u8 bits_per_word; bool rt; #define SPI_NO_TX BIT(31) /* No transmit wire */ -- 2.34.1