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[2a01:cb09:e035:4cc8:78d0:97:5365:75e1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909cabfd6esm55150315e9.15.2026.05.29.08.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 08:56:12 -0700 (PDT) From: MidG971 To: Tomeu Vizoso , Oded Gabbay Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Midgy BALON Subject: [PATCH v2 3/4] arm64: dts: rockchip: rk356x: Add NPU and its IOMMU Date: Fri, 29 May 2026 17:58:23 +0200 Message-Id: <20260529155824.3099831-4-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260529155824.3099831-1-midgy971@gmail.com> References: <20260529155824.3099831-1-midgy971@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Midgy BALON Add the RKNN core 0 and its IOMMU to the RK3568 SoC dtsi, mirroring the RK3588 pattern in rk3588-base.dtsi but with rk3568-specific clocks, resets, power domain, and a rockchip,pmu phandle required for the NPU NOC bus de-idle sequence. Both nodes remain disabled by default; boards enable them as needed. Signed-off-by: Midgy BALON --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 8893b7b6c..2c2a57ea3 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -929,6 +929,37 @@ qos_rga_wr: qos@fe158300 { reg = <0x0 0xfe158300 0x0 0x20>; }; + rknn_core_0: npu@fde40000 { + compatible = "rockchip,rk3568-rknn-core"; + reg = <0x0 0xfde40000 0x0 0x1000>, + <0x0 0xfde41000 0x0 0x1000>, + <0x0 0xfde43000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = ; + clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_PRE>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3568_PD_NPU>; + rockchip,pmu = <&pmu>; + iommus = <&rknn_mmu_0>; + status = "disabled"; + }; + + rknn_mmu_0: iommu@fde4b000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xfde4b000 0x0 0x40>; + interrupts = ; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>; + power-domains = <&power RK3568_PD_NPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + qos_npu: qos@fe180000 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe180000 0x0 0x20>; -- 2.39.5