Re: [PATCH v2 net-next 2/3] dt-bindings: dpll: add SiTime SiT9531x clock generator

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The YAML binding fails to enforce the hardware limits (number of input/output pins and PLLs) between variants claimed in the commit message.
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commit de5c539cf5b5d391a13e0203a532efbfc0d6f0d4
Author: Ali Rouhi <rouhi.ali@gmail.com>

dt-bindings: dpll: add SiTime SiT9531x clock generator

Add device tree binding documentation for the SiTime SiT95316
and SiT95317 DPLL clock generators.

> diff --git a/Documentation/devicetree/bindings/dpll/sitime,sit9531x.yaml b/Documentation/devicetree/bindings/dpll/sitime,sit9531x.yaml
> new file mode 100644
> index 0000000000000..ac88f2f0b2ae7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dpll/sitime,sit9531x.yaml
[ ... ]
> +description: |
> +  SiTime SiT95316 and SiT95317 are I2C-controlled programmable clock
> +  generators with integrated DPLL for synchronization applications.  Both
> +  variants contain four PLLs with automatic/manual reference selection,
> +  DCO frequency adjustment, and phase offset measurement via an on-chip
> +  TDC (Time-to-Digital Converter).
> +
> +  SiT95317 provides 4 inputs and 8 outputs; SiT95316 provides
> +  4 inputs and 12 outputs.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - sitime,sit95316
> +      - sitime,sit95317

[Severity: Low]
Does this binding need to enforce the hardware limits between variants that
are claimed in the description?

The description explicitly states that the SiT95317 provides 8 outputs, the
SiT95316 provides 12 outputs, and both have 4 PLLs. However, the YAML schema
does not constrain the dpll-types array to maxItems: 4, nor does it include
conditional if-then blocks to limit the logical reg property under
output-pins/pin@X based on the specific compatible string (e.g., maximum: 7
for sitime,sit95317).

Consequently, the schema will silently pass validation for device trees that
declare structurally impossible configurations (e.g., 5 PLLs or 12 outputs
for the 95317 variant). While the driver might handle these edge cases
internally, the missing constraints represent a gap in the schema validation.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260520191943.73938-1-arouhi@sitime.com?part=2