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([2a0a:ef40:ea3:3f01:2e0:4cff:fe68:285]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45ef32fabcasm11667339f8f.0.2026.05.30.09.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 May 2026 09:07:12 -0700 (PDT) From: Dawid Olesinski To: herbert@gondor.apana.org.au, davem@davemloft.net, heiko@sntech.de Cc: linux-crypto@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, clabbe@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, Dawid Olesinski Subject: [PATCH 1/4] dt-bindings: crypto: rockchip: Add RK356x/RK3588 crypto engine binding Date: Sat, 30 May 2026 17:06:42 +0100 Message-ID: <20260530160704.3453555-2-dawidro@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260530160704.3453555-1-dawidro@gmail.com> References: <20260530160704.3453555-1-dawidro@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a YAML device tree binding for the Rockchip second-generation (V2) cryptographic hardware accelerator present on the RK3568 and RK3588 SoCs. The IP block exposes AES-ECB, AES-CBC, AES-XTS block ciphers, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, MD5, and SM3 hash algorithms, each with a hardware DMA engine controlled via linked-list descriptors. The binding covers two compatible strings: - rockchip,rk3568-crypto: clocks and resets are driven directly by the non-secure CRU (accessible to Linux at EL1). - rockchip,rk3588-crypto: clocks and resets live in SECURECRU, a register bank sandboxed to TrustZone. Linux must request them through the ARM SCMI firmware interface (scmi_clk / scmi_reset), as direct MMIO access to SECURECRU from EL1 triggers a bus fault. Signed-off-by: Dawid Olesinski --- .../crypto/rockchip,rk3588-crypto.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml new file mode 100644 index 000000000000..4188ed8920db --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip cryptographic offloader + +maintainers: + - Heiko Stuebner + - Corentin Labbe + - Dawid Olesinski + +properties: + compatible: + enum: + - rockchip,rk3568-crypto + - rockchip,rk3588-crypto + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Core clock for the crypto IP internal logic + - description: AXI interconnect clock interface + - description: AHB interface clock + + clock-names: + items: + - const: core + - const: aclk + - const: hclk + + resets: + maxItems: 1 + + reset-names: + items: + - const: core + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + + crypto@fe370000 { + compatible = "rockchip,rk3588-crypto"; + reg = <0x0 0xfe370000 0x0 0x2000>; + interrupts = ; + clocks = <&scmi_clk SCMI_CRYPTO_CORE>, + <&scmi_clk SCMI_ACLK_SECURE_NS>, + <&scmi_clk SCMI_HCLK_SECURE_NS>; + clock-names = "core", "aclk", "hclk"; + resets = <&scmi_reset SCMI_SRST_CRYPTO_CORE>; + reset-names = "core"; + }; -- 2.47.3