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([2a0a:ef40:ea3:3f01:2e0:4cff:fe68:285]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45ef32fabcasm11667339f8f.0.2026.05.30.09.07.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 May 2026 09:07:19 -0700 (PDT) From: Dawid Olesinski To: herbert@gondor.apana.org.au, davem@davemloft.net, heiko@sntech.de Cc: linux-crypto@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, clabbe@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, Dawid Olesinski Subject: [PATCH 3/4] arm64: dts: rockchip: Add crypto node to rk356x-base Date: Sat, 30 May 2026 17:06:44 +0100 Message-ID: <20260530160704.3453555-4-dawidro@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260530160704.3453555-1-dawidro@gmail.com> References: <20260530160704.3453555-1-dawidro@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the device tree node for the V2 cryptographic hardware accelerator on RK356x SoCs (RK3566, RK3568). The IP block sits in the non-secure peripheral domain. Its three clocks (core, aclk, hclk) and reset line are accessible directly through the main non-secure CRU, so no firmware intermediary is required. The node is disabled by default; board files that wish to use hardware crypto offload must enable it. Signed-off-by: Dawid Olesinski --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 64bdd8b7754b..3b73a56046e7 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1171,6 +1171,18 @@ gpu_leakage: gpu-leakage@1d { }; }; + crypto: crypto@fe380000 { + compatible = "rockchip,rk3568-crypto"; + reg = <0x0 0xfe380000 0x0 0x2000>; + interrupts = ; + clocks = <&cru CLK_CRYPTO_NS_CORE>, <&cru ACLK_CRYPTO_NS>, + <&cru HCLK_CRYPTO_NS>; + clock-names = "core", "aclk", "hclk"; + resets = <&cru SRST_CRYPTO_NS_CORE>; + reset-names = "core"; + status = "disabled"; + }; + i2s0_8ch: i2s@fe400000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x0 0xfe400000 0x0 0x1000>; -- 2.47.3