Re: [PATCH v4 3/3] arm64: dts: rockchip: add Vicharak Axon board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Missing PHY Initialization for `pcie2x1l1` PCIe controller
- [Low] Alphabetical sorting violation in Makefile
--

commit dfbd817683ee0ef28e8408ee1abe3937bb3a7365
Author: Hrushiraj Gandhi <hrushirajg23@gmail.com>

arm64: dts: rockchip: add Vicharak Axon board

This commit adds initial support for the Vicharak Axon single-board computer
based on the Rockchip RK3588 SoC. It includes device tree configuration for
various peripherals such as PCIe, Ethernet, HDMI, and storage.

> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> index cb55c6b70d0e5..fcb115b02effa 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -179,6 +179,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vicharak-axon.dtb

[Severity: Low]
This isn't a bug, but should this be placed further down the list to
maintain alphabetical sorting? It looks like it is inserted between
armsom-w3 and coolpi-cm5-evb.

>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-genbook.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb

[ ... ]

> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts
> new file mode 100644
> index 0000000000000..bfc50480668e4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts

[ ... ]

> +&pcie2x1l0 {
> +	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie2_0_rst>;
> +	vpcie3v3-supply = <&vcc3v3_pcie20_sata30>;
> +	status = "okay";
> +};
> +
> +&pcie2x1l1 {
> +	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie2_1_rst>;
> +	vpcie3v3-supply = <&vcc3v3_pcie20_sata30>;
> +	status = "okay";
> +};

[Severity: High]
Does the pcie2x1l1 controller need its prerequisite PHY node enabled here?
Looking at the device tree, combphy2_psu is not marked with status = "okay",
which might cause the PCIe controller probe to defer or fail completely.

> +
> +&pcie2x1l2 {
> +	status = "disabled";
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260601151810.162173-1-hrushirajg23@gmail.com?part=3