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(180-93-184-31.ftth.glasoperator.nl [31.184.93.180]) by submission15.mail.transip.nl (Postfix) with ESMTPA id 4gTyVZ2qhtz3R3nyb; Tue, 2 Jun 2026 06:27:50 +0200 (CEST) From: Herman van Hazendonk To: sboyd@kernel.org Cc: Herman van Hazendonk , Bjorn Andersson , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] clk: qcom: gcc-msm8660: register PLL4_VOTE for LPASS Date: Tue, 2 Jun 2026 06:27:45 +0200 Message-ID: <20260602042747.277270-3-github.com@herrie.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602042747.277270-1-github.com@herrie.org> References: <20260602042747.277270-1-github.com@herrie.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: ClueGetter at submission15.mail.transip.nl DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=transip-a; d=herrie.org; t=1780374470; h=from:subject:to:cc: references:in-reply-to:date:mime-version; bh=g3ROW7hBNhkKFHDQavHcox1vYNkJIWsOzzdzMxdC0i0=; b=TVjmjVox6kZxVyyiiLost18MWfUNz9ZIB9vn5FiWh8G50PnJ5Hsm6l3m9ImMYknx0Xml88 lGL/8VI0Rj2ux3mS8uCUYi7/22TMJlCvrxkwXZFJnbR+w/NY5yJjhVpRk0Dr9aOwrx6JqC FuFDOkA0vcwvtmAJflvS3DlMNLTv01chohqo3kJCleVd9Xu1QB/6yErd/SRl4PhCgRCj9W U8qwVZoQTC4o3+//1pXUHYPeMwI/eKRtZ2XI/AFsGzBS+yOTvqyInjgN+MIF22q3dOhyZV KfRSg2hnq6ObnNVHSgdfFj/BpcmP0DXgMKpX14znj6JYlyRajr9tSEr6axb+4w== X-Report-Abuse-To: abuse@transip.nl Add the CPU-side software vote register for LPASS PLL4. PLL4 itself lives in the LCC (Low Power Audio Subsystem clock controller); GCC holds the apps-processor vote in PLL_ENA_SC0 (0x34c0) BIT(4). The LCC driver references "pll4" as the parent of its slimbus / SAIF / audio mclk roots, so without this vote PLL4 is gated off when the apps processor is the only consumer and LCC clocks silently fail to enable. Expose it as a single clk_regmap with clk_pll_vote_ops and append the dt-binding ID at the next free slot (258) after the existing PLL12 (257), so DT ABI for boards already using the prior header is preserved. Signed-off-by: Herman van Hazendonk --- drivers/clk/qcom/gcc-msm8660.c | 15 +++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8660.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c index e81b8851a786..cd392e140e95 100644 --- a/drivers/clk/qcom/gcc-msm8660.c +++ b/drivers/clk/qcom/gcc-msm8660.c @@ -54,6 +54,20 @@ static struct clk_regmap pll8_vote = { }, }; +/* PLL4 is the LPASS PLL, defined in LCC. This is the voting clock. */ +static struct clk_regmap pll4_vote = { + .enable_reg = 0x34c0, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "pll4_vote", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pll4", .name = "pll4", + }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + enum { P_PXO, P_PLL8, @@ -2543,6 +2557,7 @@ static struct clk_branch rpm_msg_ram_h_clk = { static struct clk_regmap *gcc_msm8660_clks[] = { [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, + [PLL4_VOTE] = &pll4_vote, [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, diff --git a/include/dt-bindings/clock/qcom,gcc-msm8660.h b/include/dt-bindings/clock/qcom,gcc-msm8660.h index 4777c002711a..51d2e97441c8 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8660.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8660.h @@ -264,5 +264,6 @@ #define PLL10 255 #define PLL11 256 #define PLL12 257 +#define PLL4_VOTE 258 #endif -- 2.43.0