Re: [PATCH v31 1/5] dt-bindings: i2c: Split AST2600 binding into a new YAML

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The dt-binding YAML example uses incorrect clock and reset definitions for the AST2600 SoC, which maps the I2C controller to the wrong hardware lines.
- [Medium] The newly introduced AST2600 I2C binding schema file is not registered in the MAINTAINERS file under the ASPEED I2C CONTROLLER DRIVER section.
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commit ac52f88742bbf18c3be4d1bbc7f7a9f7bd2850ae
Author: Ryan Chen <ryan_chen@aspeedtech.com>

dt-bindings: i2c: Split AST2600 binding into a new YAML

The AST2600 I2C controller introduces a completely new register layout
with separate controller and target register blocks. This commit moves
the AST2600 I2C binding into a dedicated aspeed,ast2600-i2c.yaml schema
and adjusts for AST2600-specific requirements.

[Severity: Medium]
This patch splits out a new file but misses adding it to the maintainer
index.

MAINTAINERS:
ARM/ASPEED I2C DRIVER
...
F:	Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml

Since there is no wildcard covering the directory, will get_maintainer.pl
fail to match aspeed,ast2600-i2c.yaml to the ASPEED I2C maintainers?
This regression means the primary maintainers might not be automatically
copied on future patches modifying these bindings.

> diff --git a/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml
> new file mode 100644
> index 0000000000000..abc614315dffb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/clock/aspeed-clock.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    i2c@80 {
> +        compatible = "aspeed,ast2600-i2c-bus";
> +        reg = <0x80 0x80>, <0xc00 0x20>;
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        clocks = <&syscon ASPEED_CLK_APB>;
> +        resets = <&syscon ASPEED_RESET_I2C>;

[Severity: Medium]
Are these the correct clock and reset definitions for the AST2600 SoC?

The example includes the legacy <dt-bindings/clock/aspeed-clock.h> header
where ASPEED_CLK_APB evaluates to 26 and ASPEED_RESET_I2C evaluates to 7.

For the AST2600 hardware, clock index 26 maps to ASPEED_CLK_GATE_UART5CLK
and the correct I2C reset index is 34.

If this example is copied into an AST2600 device tree, will the driver
toggle the UART5 clock gate and the wrong reset line? This regression could
cause the I2C bus to fail initialization and disrupt UART5 operations.

Should this use <dt-bindings/clock/ast2600-clock.h> instead?

> +        clock-frequency = <100000>;
> +        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> +    };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260603-upstream_i2c-v31-0-ba7a02714f22@aspeedtech.com?part=1