Re: [PATCH net v3 2/2] dt-bindings: net: updated interrupt type to be active low, level triggered

[Conor Dooley <conor@kernel.org>]

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On Thu, Jun 04, 2026 at 03:21:47PM +0000, Selvamani Rajagopal wrote:
> > Subject: Re: [PATCH net v3 2/2] dt-bindings: net: updated interrupt type to be active low,
> > level triggered
> > 
> > Hi Conor & Selvamani,

To be clear, my angle here is making sure that the microchip device is
not deviant from the spec. I don't know or care about this hardware in
particular.
I just made the assumption that what was in the example worked, and
wanted clarification that what the example was changed to actually
reflected something else that worked on the hardware in question before
I gave an ack. I'm a dt-binding maintainer, not someone with knowledge
of these devices.

> > 
> [.]
> > One possible alternative could be to use a threaded IRQ handler with
> > IRQF_ONESHOT, where the IRQ line is disabled until the handler
> > completes, and sleeping is allowed. In that case, we could perform the
> > SPI transfer in the threaded handler to send the data header and
> > deassert the interrupt, while deferring the remaining work to a separate
> > kthread (the current SPI thread). However, I have not yet tried this
> > implementation, so I cannot comment on its behavior or effectiveness
> > without implementing and testing it.
> 
> I can test this in my setup.
> 
> > 
> > I may be missing something here and am trying to clarify my
> > understanding. I am also curious why this issue reproduces on our system
> > but does not appear in Selvamani’s setup with an active‑low level
> > interrupt configuration. If possible, could you share details of your
> > setup and how the testing is being performed?
> 
> My setup is similar to yours. We have Raspberry Pi boards (P-4 & Pi-5) connected
> to our MAC-PHY evaluation board. As you could see in my patch submissions, 
> there are no changes to oa_tc6.c in the way interrupts are handled.
> 
> > 
> > Best regards,
> > Parthiban V
> > >
> > >>
> > >> Cheers,
> > >> Conor.
> > >>
> > >>>
> 

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