From: sashiko-bot@kernel.org
To: hongxing.zhu@oss.nxp.com
Cc: imx@lists.linux.dev, conor+dt@kernel.org, robh@kernel.org,
devicetree@vger.kernel.org, Frank.Li@kernel.org
Subject: Re: [PATCH v1 1/2] arm64: dts: imx94: Correct PCIe outbound address space configuration
Date: Thu, 04 Jun 2026 02:48:19 +0000 [thread overview]
Message-ID: <20260604024819.B43971F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260604023821.134372-1-hongxing.zhu@oss.nxp.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Incomplete Fix: The commit fails to apply the PCIe outbound memory range and I/O space fixes to the identical `pcie1` controller.
--
commit c0fba22963c11d85152a1282d3153eaca25dcb81
Author: Richard Zhu <hongxing.zhu@nxp.com>
arm64: dts: imx94: Correct PCIe outbound address space configuration
Fix the PCIe outbound memory ranges for both pcie0 controllers on i.MX94.
> diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
> index a6cb5a6e848b3..1f9035e6cf159 100644
> --- a/arch/arm64/boot/dts/freescale/imx94.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
> @@ -1374,8 +1374,9 @@ pcie0: pcie@4c300000 {
> <0 0x4c360000 0 0x10000>,
> <0 0x4c340000 0 0x4000>;
> reg-names = "dbi", "config", "atu", "app";
> - ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> - <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>;
> + ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
> + <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
> + <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
[Severity: High]
This isn't a bug introduced by this patch, but should the identical fix
be applied to the pcie1 controller as well?
Looking at arch/arm64/boot/dts/freescale/imx943.dtsi, the pcie1 node
retains the old outbound mapping:
pcie1: pcie@4c380000 {
...
ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
<0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>;
The 1MB I/O region for pcie1 is mapped at CPU physical address 0x8_8ff00000.
This falls inside the 256MB hardware ECAM decoding boundary (0x8_80000000 to
0x8_90000000), which will likely be routed as configuration space rather than
outbound I/O. This breaks translation for any attached PCIe devices requiring
I/O space.
Additionally, pcie1's memory window remains artificially restricted to 2GB
instead of the supported 4GB.
Would it make sense to duplicate this ranges fix for pcie1 using its
respective 0xa_00000000 outbound address window to completely resolve the
issue for the SoC?
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260604023821.134372-1-hongxing.zhu@oss.nxp.com?part=1
prev parent reply other threads:[~2026-06-04 2:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-04 2:38 [PATCH v1 1/2] arm64: dts: imx94: Correct PCIe outbound address space configuration hongxing.zhu
2026-06-04 2:38 ` [PATCH v1 2/2] arm64: dts: imx943: " hongxing.zhu
2026-06-04 2:48 ` sashiko-bot [this message]
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