From: Zi-Yu Chen <zychennvt@gmail.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org
Cc: ychuang3@nuvoton.com, schung@nuvoton.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Zi-Yu Chen <zychennvt@gmail.com>
Subject: [PATCH] arm64: dts: nuvoton: ma35d1: add CAN nodes
Date: Thu, 4 Jun 2026 14:01:04 +0800 [thread overview]
Message-ID: <20260604060104.1662700-1-zychennvt@gmail.com> (raw)
Add controller nodes for the four Bosch M_CAN blocks found on the
Nuvoton MA35D1 SoC.
Additionally, configure pinctrl and enable CAN1 and CAN3 on the
MA35D1 SOM board.
Signed-off-by: Zi-Yu Chen <zychennvt@gmail.com>
---
.../boot/dts/nuvoton/ma35d1-som-256m.dts | 26 ++++++++
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 60 +++++++++++++++++++
2 files changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
index f6f20a17e501..1b8ea14d3446 100644
--- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
@@ -37,6 +37,18 @@ clk_hxt: clock-hxt {
};
};
+&can1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+};
+
+&can3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can3>;
+};
+
&clk {
assigned-clocks = <&clk CAPLL>,
<&clk DDRPLL>,
@@ -56,6 +68,20 @@ &clk {
};
&pinctrl {
+ can-grp {
+ pinctrl_can1: can1-pins {
+ nuvoton,pins = <11 14 4>,
+ <11 15 4>;
+ bias-disable;
+ };
+
+ pinctrl_can3: can3-pins {
+ nuvoton,pins = <11 10 3>,
+ <11 11 3>;
+ bias-disable;
+ };
+ };
+
uart-grp {
pinctrl_uart0: uart0-pins {
nuvoton,pins = <4 14 1>,
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
index e51b98f5bdce..584dd8d44701 100644
--- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
@@ -244,6 +244,66 @@ gpion: gpio@340 {
};
};
+ can0: can@403c0000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x403c0000 0x0 0x200>, <0x0 0x403c0200 0x0 0x2000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clk HCLK3>, <&clk CAN0_GATE>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&clk APLL>, <&clk CAN0_DIV>;
+ assigned-clock-rates = <200000000>, <50000000>;
+ bosch,mram-cfg = <0x0 4 4 32 32 32 8 8>;
+ status = "disabled";
+ };
+
+ can1: can@403d0000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x403d0000 0x0 0x200>, <0x0 0x403d0200 0x0 0x2000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clk HCLK3>, <&clk CAN1_GATE>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&clk APLL>, <&clk CAN1_DIV>;
+ assigned-clock-rates = <200000000>, <50000000>;
+ bosch,mram-cfg = <0x0 4 4 32 32 32 8 8>;
+ status = "disabled";
+ };
+
+ can2: can@403e0000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x403e0000 0x0 0x200>, <0x0 0x403e0200 0x0 0x2000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clk HCLK3>, <&clk CAN2_GATE>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&clk APLL>, <&clk CAN2_DIV>;
+ assigned-clock-rates = <200000000>, <50000000>;
+ bosch,mram-cfg = <0x0 4 4 32 32 32 8 8>;
+ status = "disabled";
+ };
+
+ can3: can@403f0000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x403f0000 0x0 0x200>, <0x0 0x403f0200 0x0 0x2000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clk HCLK3>, <&clk CAN3_GATE>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&clk APLL>, <&clk CAN3_DIV>;
+ assigned-clock-rates = <200000000>, <50000000>;
+ bosch,mram-cfg = <0x0 4 4 32 32 32 8 8>;
+ status = "disabled";
+ };
+
uart0: serial@40700000 {
compatible = "nuvoton,ma35d1-uart";
reg = <0x0 0x40700000 0x0 0x100>;
--
2.34.1
next reply other threads:[~2026-06-04 6:01 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-04 6:01 Zi-Yu Chen [this message]
2026-06-04 6:11 ` [PATCH] arm64: dts: nuvoton: ma35d1: add CAN nodes sashiko-bot
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