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From: sashiko-bot@kernel.org
To: "Benoît Monin" <benoit.monin@bootlin.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v8 5/9] clk: eyeq: Prefix the PLL registers with the PLL type
Date: Thu, 04 Jun 2026 13:36:13 +0000	[thread overview]
Message-ID: <20260604133615.56C5D1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260604-clk-eyeq7-v8-5-53f618174cf6@bootlin.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Using readq() on addresses that are not 8-byte aligned will trigger hardware alignment faults on 64-bit architectures.
--

commit bf5bd431a86c5690b223e75ad314eb6d7388384c
Author: Benoît Monin <benoit.monin@bootlin.com>

clk: eyeq: Prefix the PLL registers with the PLL type

This commit renames the PLL registers to make room for other PLL types
present in the eyeQ7H. It also moves the register access inside the
parsing function to deduplicate code across call sites.

> diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
> --- a/drivers/clk/clk-eyeq.c
> +++ b/drivers/clk/clk-eyeq.c

[ ... ]

> @@ -162,34 +162,40 @@ static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div)
>  	*div >>= shift;
>  }
>  
> -static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
> -				   unsigned long *div, unsigned long *acc)
> +static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
> +			       unsigned long *div, unsigned long *acc)
>  {
>  	unsigned long spread;
> +	u32 r0, r1;
> +	u64 val;
>  
> -	if (r0 & PCSR0_BYPASS) {
> +	val = readq(base);

[Severity: High]
This is a pre-existing issue, but will this readq() trigger a hardware
alignment fault on ARM64?

The PLL registers passed as the base address (such as 0x02C, 0x034, 0x03C,
and 0x044) are 4-byte aligned, but not 8-byte aligned. On ARM64 platforms
like EyeQ6, performing a 64-bit load instruction via readq() on unaligned
device memory violates architectural rules and typically causes a
synchronous external abort.

Would it be safer to replace this with two readl() calls to avoid
alignment issues?

> +	r0 = val;
> +	r1 = val >> 32;
>  
> -	if (!(r0 & PCSR0_PLL_LOCKED))
> +	if (r0 & FRACG_PCSR0_BYPASS) {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260604-clk-eyeq7-v8-0-53f618174cf6@bootlin.com?part=5

  reply	other threads:[~2026-06-04 13:36 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-04 13:26 [PATCH v8 0/9] Add clock and reset support for Mobileye EyeQ7H Benoît Monin
2026-06-04 13:26 ` [PATCH v8 1/9] dt-bindings: soc: mobileye: Add EyeQ7H OLB Benoît Monin
2026-06-04 13:26 ` [PATCH v8 2/9] reset: eyeq: Add EyeQ7H compatibles Benoît Monin
2026-06-04 13:26 ` [PATCH v8 3/9] clk: fixed-factor: Rework initialization with parent clocks Benoît Monin
2026-06-04 13:26 ` [PATCH v8 4/9] clk: fixed-factor: Export __clk_hw_register_fixed_factor() Benoît Monin
2026-06-04 13:26 ` [PATCH v8 5/9] clk: eyeq: Prefix the PLL registers with the PLL type Benoît Monin
2026-06-04 13:36   ` sashiko-bot [this message]
2026-06-04 13:26 ` [PATCH v8 6/9] clk: eyeq: Introduce a generic clock type Benoît Monin
2026-06-04 13:51   ` sashiko-bot
2026-06-04 13:26 ` [PATCH v8 7/9] clk: eyeq: Convert clocks declaration to eqc_clock Benoît Monin
2026-06-04 13:44   ` sashiko-bot
2026-06-04 13:26 ` [PATCH v8 8/9] clk: eyeq: Drop PLL, dividers, and fixed factors structs Benoît Monin
2026-06-04 13:26 ` [PATCH v8 9/9] clk: eyeq: Add EyeQ7H compatibles Benoît Monin
2026-06-04 13:43   ` sashiko-bot

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