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Fri, 5 Jun 2026 03:23:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CB.mail.protection.outlook.com (10.167.240.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.5 via Frontend Transport; Fri, 5 Jun 2026 03:23:39 +0000 Received: from cix (unknown [172.18.64.61]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 7E9FC408426D; Fri, 5 Jun 2026 11:23:37 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, gary.yang@cixtech.com Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang Subject: [PATCH v2 0/5] Add Cix Sky1 AUDSS clock and reset support Date: Fri, 5 Jun 2026 11:22:20 +0800 Message-ID: <20260605032225.523669-1-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CB:EE_|SI2PR06MB5170:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 598dd0d8-5e11-4c22-a734-08dec2b1d6aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700016|56012099006|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bsh69wu+y+PIV5dTKOCIqETUkN1tXoqtvibvZinSiVHFpVZ9sXCDVjrDtdUqo8595Kx/X5JmA8I4tYQkg6gl8ONjo4CmfTSNEu6p8GdLrH/DuNu3CLxU4AVfDXE9bvQKE12RKQxZ3u9HV7tomOS/6KEnN97UBTTbBpU0yC7LV5AZD5AY0J5jW/qKN67D9p69Px+ruS2tBMx8+ju1F2K3yct7g9Ns6w7zjyDti+oda07CkiTB1I2mlY5Rac7F2wVQRUcOodswnhF/4LUEYLHwf2pUfQvfPdECttmFTYXFAyBzVrgYoaNe30WSRm10cxLiNcgpThGCQGgz4gSG0bEqnnsaLvpWmpd7//G7gkZeBdTgnswqW59sj2mKT5xiWIKqHYpXSbm4LYMKOEL3KdA+nhEq12xEgZqvlnO047v35ODGHGx1WVHUVwju8olxN9v+ X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 03:23:39.8012 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 598dd0d8-5e11-4c22-a734-08dec2b1d6aa X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CB.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SI2PR06MB5170 From: Joakim Zhang This patch set adds the clock and reset support for AUDSS. The AUDSS groups audio-related peripherals (HDA, I2S, DSP, DMA, mailboxes, watchdog, timer, etc.) behind a single Clock and Reset Unit (CRU) register block. I know the best approach would be to separate reset and clock into different patches for review. However, here the relationship between them as parent and child nodes is coupled, which makes it easier to understand and explain. Therefore, they are sent for review in a single patch set, and the code is based on the latest clk-next branch. ChangeLogs: v1->v2: * remove audss_rst device node since it doesn't has resource, and move to reset-sky1.c driver. * remove hda related which would be sent after this patch set accepted * soc componnet is okay by default from dtsi * fix for audss clk driver: * remove "comment "Clock options for Cixtech audss:"" * add select MFD_SYSCON * move lock and clk_data into struct sky1_audss_clks_priv * const char *name -> const char * const * name * remove CLK_GET_RATE_NOCACHE * divicer -> divider * Reverse Christmas tree order * return reg ? 1 : 0; -> return !!reg; * return ERR_CAST(hw); -> return hw; * of_device_get_match_data(dev) -> device_get_match_data() * add lock from runtime_suspend/resume * loop to more mailing lists Joakim Zhang (5): dt-bindings: soc: cix,sky1-system-control: add audss system control reset: cix: add audss support to sky1 reset driver dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller clk: cix: add sky1 audss clock controller arm64: dts: cix: sky1: add audss system control .../bindings/clock/cix,sky1-audss-clock.yaml | 92 ++ .../soc/cix/cix,sky1-system-control.yaml | 39 +- arch/arm64/boot/dts/cix/sky1.dtsi | 28 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/cix/Kconfig | 16 + drivers/clk/cix/Makefile | 3 + drivers/clk/cix/clk-sky1-audss.c | 1129 +++++++++++++++++ drivers/reset/reset-sky1.c | 36 +- include/dt-bindings/clock/cix,sky1-audss.h | 62 + .../reset/cix,sky1-audss-system-control.h | 27 + 11 files changed, 1427 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml create mode 100644 drivers/clk/cix/Kconfig create mode 100644 drivers/clk/cix/Makefile create mode 100644 drivers/clk/cix/clk-sky1-audss.c create mode 100644 include/dt-bindings/clock/cix,sky1-audss.h create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h -- 2.50.1