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Fri, 5 Jun 2026 03:23:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000C9.mail.protection.outlook.com (10.167.240.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.5 via Frontend Transport; Fri, 5 Jun 2026 03:23:44 +0000 Received: from cix (unknown [172.18.64.61]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 2E374408426D; Fri, 5 Jun 2026 11:23:41 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, gary.yang@cixtech.com Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang Subject: [PATCH v2 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller Date: Fri, 5 Jun 2026 11:22:23 +0800 Message-ID: <20260605032225.523669-4-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260605032225.523669-1-joakim.zhang@cixtech.com> References: <20260605032225.523669-1-joakim.zhang@cixtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C9:EE_|KU2PPF0C4CE1E54:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: a7ececbb-b89f-4b78-5133-08dec2b1d9a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700016|22082099003|18002099003|6133799003|56012099006|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qNXRu0k1tvleKmRP373oPqxKTsvmgHQVnwDv51lTKUASsD3wXvWulNDkAldygirBvi1rwAHiIa1dw+FKScIntle6tp/Td6ejsfcnTVaW1XHSetiLW+3p3FaD/xP++/gD9YiunPEn+9D+2jbIo5EiP76zwaLeZJan64hW0etyDv5cWUrpUrTNQc7MGyZvuieN6sl/VpQK0BSVVyn8c2rDWL4gXwBhfn60Km8fOTMGTIMbqt2qcE3ZheOMeQH6Ol63Y2vREkjCyInZKCD3KaA8kqxgnFdIHQtbbkh8hC9YEooN8OCwNzO99NDTPPKrnFAE4H+t+MQSHGSabTBt+cYuQrHYSjM/uW6Lt70BpIPJy3FDY9CQuSfAoZDN0T62oRSU3MJlhDEskvcRfRAgE2R8wilRAI1tLFp03pKW8eN0XXc30ajQHNQTOIN3w/vftNSr X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 03:23:44.7004 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7ececbb-b89f-4b78-5133-08dec2b1d9a4 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C9.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KU2PPF0C4CE1E54 From: Joakim Zhang The AUDSS CRU contains an internal clock tree of muxes, dividers and gates for DSP, I2S, HDA, DMAC and related blocks. The clock provider is a child node of the cix,sky1-audss-system-control syscon and accesses registers through the parent MMIO region. Add the devicetree binding for cix,sky1-audss-clock and clock indices in include/dt-bindings/clock/cix,sky1-audss.h. Document the parent syscon indices. Signed-off-by: Joakim Zhang --- .../bindings/clock/cix,sky1-audss-clock.yaml | 92 +++++++++++++++++++ include/dt-bindings/clock/cix,sky1-audss.h | 62 +++++++++++++ 2 files changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml create mode 100644 include/dt-bindings/clock/cix,sky1-audss.h diff --git a/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml new file mode 100644 index 000000000000..22b4cc72f395 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 audio subsystem clock controller + +maintainers: + - Joakim Zhang + +description: | + Clock provider for the Cix Sky1 audio subsystem (AUDSS). + + This node is a child of a cix,sky1-audss-system-control MFD/syscon node + (see cix,sky1-system-control.yaml). It does not have a reg property; clock + mux, divider and gate fields are accessed through the parent register block. + + Software reset lines for AUDSS blocks are exposed on the parent syscon via + #reset-cells. Reset indices are defined in + include/dt-bindings/reset/cix,sky1-audss-system-control.h. + + Six SoC-level reference clocks listed in clocks/clock-names feed the AUDSS + clock tree. The provider exposes the internal AUDSS clocks to other devices + via #clock-cells; indices are defined in cix,sky1-audss.h. + +properties: + compatible: + const: cix,sky1-audss-clock + + '#clock-cells': + const: 1 + description: + Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss.h. + + clocks: + minItems: 6 + maxItems: 6 + description: + Six SoC-level audio reference clocks that feed the audio subsystem, + in the same order as clock-names. + + clock-names: + items: + - const: audio_clk0 + - const: audio_clk1 + - const: audio_clk2 + - const: audio_clk3 + - const: audio_clk4 + - const: audio_clk5 + + resets: + maxItems: 1 + description: Audio subsystem NoC (or bus) reset line. + + power-domains: + maxItems: 1 + description: Audio subsystem power domain. + +required: + - compatible + - '#clock-cells' + - clocks + - clock-names + - resets + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + audss_syscon: system-controller@7110000 { + compatible = "cix,sky1-audss-system-control", "simple-mfd", "syscon"; + reg = <0x7110000 0x10000>; + #reset-cells = <1>; + + audss_clk: clock-controller { + compatible = "cix,sky1-audss-clock"; + power-domains = <&smc_devpd 0>; + #clock-cells = <1>; + clocks = <&scmi_clk CLK_TREE_AUDIO_CLK0>, <&scmi_clk CLK_TREE_AUDIO_CLK1>, + <&scmi_clk CLK_TREE_AUDIO_CLK2>, <&scmi_clk CLK_TREE_AUDIO_CLK3>, + <&scmi_clk CLK_TREE_AUDIO_CLK4>, <&scmi_clk CLK_TREE_AUDIO_CLK5>; + clock-names = "audio_clk0", "audio_clk1", "audio_clk2", + "audio_clk3", "audio_clk4", "audio_clk5"; + resets = <&src SKY1_AUDIO_HIFI5_NOC_RESET_N>; + }; + }; diff --git a/include/dt-bindings/clock/cix,sky1-audss.h b/include/dt-bindings/clock/cix,sky1-audss.h new file mode 100644 index 000000000000..041f9daa1ee4 --- /dev/null +++ b/include/dt-bindings/clock/cix,sky1-audss.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_CIX_SKY1_AUDSS_H +#define _DT_BINDINGS_CLK_CIX_SKY1_AUDSS_H + +#define CLK_AUD_CLK4_DIV2 0 +#define CLK_AUD_CLK4_DIV4 1 +#define CLK_AUD_CLK5_DIV2 2 + +#define CLK_DSP_CLK 3 +#define CLK_DSP_BCLK 4 +#define CLK_DSP_PBCLK 5 + +#define CLK_SRAM_AXI 6 + +#define CLK_HDA_SYS 7 +#define CLK_HDA_HDA 8 + +#define CLK_DMAC_AXI 9 + +#define CLK_WDG_APB 10 +#define CLK_WDG_WDG 11 + +#define CLK_TIMER_APB 12 +#define CLK_TIMER_TIMER 13 + +#define CLK_MB_0_APB 14 /* MB0: ap->dsp */ +#define CLK_MB_1_APB 15 /* MB1: dsp->ap */ + +#define CLK_I2S0_APB 16 +#define CLK_I2S1_APB 17 +#define CLK_I2S2_APB 18 +#define CLK_I2S3_APB 19 +#define CLK_I2S4_APB 20 +#define CLK_I2S5_APB 21 +#define CLK_I2S6_APB 22 +#define CLK_I2S7_APB 23 +#define CLK_I2S8_APB 24 +#define CLK_I2S9_APB 25 +#define CLK_I2S0 26 +#define CLK_I2S1 27 +#define CLK_I2S2 28 +#define CLK_I2S3 29 +#define CLK_I2S4 30 +#define CLK_I2S5 31 +#define CLK_I2S6 32 +#define CLK_I2S7 33 +#define CLK_I2S8 34 +#define CLK_I2S9 35 + +#define CLK_MCLK0 36 +#define CLK_MCLK1 37 +#define CLK_MCLK2 38 +#define CLK_MCLK3 39 +#define CLK_MCLK4 40 + +#define AUDSS_MAX_CLKS 41 + +#endif -- 2.50.1