Re: [PATCH 1/2] dt-bindings: pinctrl: tegra238: add missing AON pin groups

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added drive groups are completely unsorted, directly contradicting the explicit ordering constraint defined in the YAML comment.
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commit 5b9124b6ede7db6d75188db397f7ab63141b1fc6
Author: Prathamesh Shete <pshete@nvidia.com>

dt-bindings: pinctrl: tegra238: add missing AON pin groups

Add 24 pin groups, and their matching drive groups, on ports EE, FF,
GG and HH to the Tegra238 AON pinmux binding. These groups are present
on the AON pin controller, so device trees that mux these pins through
it validate against the schema.

> diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml
> index ab9264d87c88e..2b2e1a82880e0 100644
> --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml
> @@ -38,8 +38,16 @@ patternProperties:
[ ... ]
> -                    # drive groups (ordered PAA, PBB, PCC, PDD, PEE)
> +                    # drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH)
>                      drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
>                      drive_vcomp_alert_paa2, drive_pwm1_paa3,
[ ... ]
> @@ -53,7 +61,19 @@ patternProperties:
>                      drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
>                      drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
>                      drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
> -                    drive_pwm3_pee0, drive_pwm7_pee1 ]
> +                    drive_pwm3_pee0, drive_pwm7_pee1,
> +                    drive_soc_gpio49_pee2, drive_soc_gpio50_pee4,
> +                    drive_soc_gpio82_pee3, drive_soc_gpio71_pff2,
> +                    drive_soc_gpio76_pff7, drive_soc_gpio74_pff5,
> +                    drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,

[Severity: Low]
Does this order violate the comment preceding the drive groups?

The comment explicitly specifies that the drive groups should be ordered by
port (PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH).

However, the newly added drive groups appear to be jumbled and not ordered
by port. For example, drive_soc_gpio86_phh3 appears before
drive_soc_gpio72_pff3, and drive_soc_gpio76_pff7 appears before
drive_soc_gpio74_pff5.

Should these be sorted sequentially by port to match the documented
formatting constraint?

> +                    drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6,
> +                    drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5,
> +                    drive_soc_gpio73_pff4, drive_soc_gpio70_pff1,
> +                    drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0,
> +                    drive_uart5_tx_pgg7, drive_uart5_rx_phh0,
> +                    drive_uart2_tx_pgg2, drive_uart2_rx_pgg3,
> +                    drive_uart2_cts_pgg5, drive_uart2_rts_pgg4,
> +                    drive_uart5_cts_phh2, drive_uart5_rts_phh1 ]
>  
>  required:
>    - compatible

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Sashiko AI review · https://sashiko.dev/#/patchset/20260608094122.1245189-1-pshete@nvidia.com?part=1