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From: sashiko-bot@kernel.org
To: "Mohammad Rafi Shaik" <mohammad.rafi.shaik@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH v1 2/3] ASoC: qcom: lpass-rx-macro: Add shikra compatible
Date: Mon, 08 Jun 2026 17:43:16 +0000	[thread overview]
Message-ID: <20260608174316.77DCA1F00898@smtp.kernel.org> (raw)
In-Reply-To: <20260608172023.2965292-3-mohammad.rafi.shaik@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Race condition on `rx_mclk_users` reference counter between ALSA DAPM and the common clock framework.
--

commit 7e806c720683c8e53a8ab54c5095d11f817bb75e
Author: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>

ASoC: qcom: lpass-rx-macro: Add shikra compatible

This commit adds shikra RX macro compatible data and hooks it into the
existing LPASS codec v4.0 flow. It maps codec v4.0 to the 2.5+ RX register
handling paths, and enables the FS counter bypass bit during MCLK enable
when requested.

> diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c
> index 6233aa9f5bc6d..3a3dec6b14cda 100644
> --- a/sound/soc/codecs/lpass-rx-macro.c
> +++ b/sound/soc/codecs/lpass-rx-macro.c
[ ... ]
> @@ -2043,6 +2045,11 @@ static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable)
>  					   CDC_RX_CLK_MCLK2_ENABLE);
>  			regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
>  					   CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00);
> +
> +			if (rx->bypass_fs_control)
> +				regmap_update_bits(regmap,
> +						   CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
> +						   0x80, 0x80);

[Severity: High]
This is a pre-existing issue, but is there a race condition on the
rx->rx_mclk_users reference counter in rx_macro_mclk_enable() in
sound/soc/codecs/lpass-rx-macro.c?

The rx_macro_mclk_enable() function checks and modifies the rx->rx_mclk_users
reference counter while updating MCLK hardware registers. Since this is called
from two disjoint locking domains, the ALSA DAPM event callback
(rx_macro_mclk_event) holding the ALSA dapm_mutex, and the clock framework
callbacks (swclk_gate_enable or swclk_gate_disable) holding the clock
framework's prepare_lock, could concurrent executions clobber the reference
count?

Without a shared lock or atomic variable protecting rx_mclk_users, could this
data race result in the underlying hardware MCLK being incorrectly disabled
while still in use (causing audio failures or SoundWire bus hangs), or never
disabled (causing power leaks)?

>  			regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
>  					   CDC_RX_FS_MCLK_CNT_EN_MASK,
>  					   CDC_RX_FS_MCLK_CNT_ENABLE);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260608172023.2965292-1-mohammad.rafi.shaik@oss.qualcomm.com?part=2

  reply	other threads:[~2026-06-08 17:43 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-08 17:20 [PATCH v1 0/3] ASoC: qcom: Add shikra LPASS RX/VA macro support Mohammad Rafi Shaik
2026-06-08 17:20 ` [PATCH v1 1/3] ASoC: dt-bindings: qcom: Add Shikra rx and va macro codecs Mohammad Rafi Shaik
2026-06-08 17:29   ` sashiko-bot
2026-06-08 17:20 ` [PATCH v1 2/3] ASoC: qcom: lpass-rx-macro: Add shikra compatible Mohammad Rafi Shaik
2026-06-08 17:43   ` sashiko-bot [this message]
2026-06-08 17:20 ` [PATCH v1 3/3] ASoC: qcom: lpass-va-macro: " Mohammad Rafi Shaik
2026-06-08 17:52   ` sashiko-bot

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