From: sashiko-bot@kernel.org
To: "Atish Patra" <atish.patra@linux.dev>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v6 06/21] dt-bindings: riscv: add Smcntrpmf ISA extension description
Date: Tue, 09 Jun 2026 06:09:14 +0000 [thread overview]
Message-ID: <20260609060915.6C7461F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260608-counter_delegation-v6-6-285b72ed65a9@meta.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The `smcntrpmf` extension is inserted in the wrong alphabetical order.
- [Low] The description incorrectly refers to `Smcntrpmf` as a 'supervisor-level' extension.
--
commit 9fd028f70a33e1a78db2f635eed4200c33b6b90d
Author: Atish Patra <atishp@rivosinc.com>
dt-bindings: riscv: add Smcntrpmf ISA extension description
Add the description for the Smcntrpmf ISA extension.
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 4be557dc215de..ece3edccee42c 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -189,6 +189,12 @@ properties:
> mechanism in M-mode as ratified in the 20240326 version of the
> privileged ISA specification.
>
> + - const: smcntrpmf
[Severity: Low]
Is this inserted in the correct alphabetical order?
The multi-letter extensions list in this file explicitly requires entries to be
sorted alphanumerically. Alphabetically, smcntrpmf ("c-n") should come before
the preceding extension (smcsrind, "c-s").
> + description: |
> + The standard Smcntrpmf supervisor-level extension for the machine mode
[Severity: Low]
Is "supervisor-level" accurate here?
In the RISC-V ISA naming convention, the "Sm" prefix denotes a standard
machine-level extension, while "Ss" denotes a supervisor-level extension.
Calling it a "supervisor-level extension for the machine mode" seems
contradictory. Could this be a copy-paste error?
> + to enable privilege mode filtering for cycle and instret counters as
> + ratified in the 20240326 version of the privileged ISA specification.
> +
> - const: smmpm
> description: |
> The standard Smmpm extension for M-mode pointer masking as
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260608-counter_delegation-v6-0-285b72ed65a9@meta.com?part=6
next prev parent reply other threads:[~2026-06-09 6:09 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-09 6:01 [PATCH v6 00/21] Add Counter delegation ISA extension support Atish Patra
2026-06-09 6:01 ` [PATCH v6 01/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2026-06-09 6:01 ` [PATCH v6 02/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2026-06-09 6:01 ` [PATCH v6 03/21] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2026-06-09 6:09 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 04/21] RISC-V: Define indirect CSR access helpers Atish Patra
2026-06-09 6:15 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 05/21] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-06-09 6:01 ` [PATCH v6 06/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-06-09 6:09 ` sashiko-bot [this message]
2026-06-09 6:01 ` [PATCH v6 07/21] RISC-V: Add Sscfg extension CSR definition Atish Patra
2026-06-09 6:01 ` [PATCH v6 08/21] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-06-09 6:14 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 09/21] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-06-09 6:12 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 10/21] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-06-09 6:18 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 11/21] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-06-09 6:17 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 12/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-06-09 6:16 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 13/21] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-06-09 6:23 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 14/21] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-06-09 6:33 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 15/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-06-09 6:23 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 16/21] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-06-09 6:21 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 17/21] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-06-09 6:22 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 18/21] tools/perf: Support event code for arch standard events Atish Patra
2026-06-09 6:18 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 19/21] tools/perf: Add RISC-V CounterIDMask event field Atish Patra
2026-06-09 6:01 ` [PATCH v6 20/21] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Atish Patra
2026-06-09 6:17 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 21/21] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path Atish Patra
2026-06-09 6:20 ` sashiko-bot
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