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From: sashiko-bot@kernel.org
To: "Yunhui Cui" <cuiyunhui@bytedance.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 2/3] riscv: track effective hardware PTE A/D updating
Date: Tue, 09 Jun 2026 13:16:20 +0000	[thread overview]
Message-ID: <20260609131621.3541C1F00898@smtp.kernel.org> (raw)
In-Reply-To: <20260609130021.99899-3-cuiyunhui@bytedance.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect global ISA extension check prevents FWFT enablement on asymmetric SVADE/SVADU systems.
--

commit f3d7c0060d5bf449bef26605d30b6a4b56780451
Author: Yunhui Cui <cuiyunhui@bytedance.com>
Subject: riscv: track effective hardware PTE A/D updating

This commit separates the tracking of hardware PTE A/D updating from SVADU
discovery. It enables Firmware Features (FWFT) on all online harts before
globally advertising the feature, and requires secondary harts to enable it
before they are marked online.

> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
[ ... ]
> @@ -287,15 +291,88 @@ static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,
>  static int __init riscv_hw_pte_ad_updating_init(void)
>  {
>  	bool has_svade, has_svadu;
>  	int ret;
>  
>  	has_svade = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADE);
>  	has_svadu = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
>  
>  	if (!has_svadu)
>  		return 0;
>  
>  	if (has_svade) {
>  		riscv_hw_pte_ad_updating_requires_fwft = true;
>  		ret = riscv_set_online_hw_pte_ad_updating(true);

[Severity: High]
Since riscv_has_extension_unlikely checks the global intersection of
extensions, will has_svade evaluate to false on an asymmetric system where
some CPUs support both SVADE and SVADU, but others only support SVADU?

If has_svade evaluates to false, FWFT enablement is skipped here, but
riscv_set_hw_pte_ad_updating is unconditionally called at the end of this
function. Could this cause the kernel to assume hardware A/D tracking is
active globally, even though CPUs with both extensions would remain in their
default software-managed SVADE mode?

If the kernel incorrectly assumes hardware A/D tracking is active, would this
cause arch_has_hw_pte_young to return true and erroneously expose the SVADU
extension to KVM guests? It seems like this could lead to unexpected VS-stage
page faults and guest crashes if the underlying host CPU traps on missing A/D
bits while the guest OS expects hardware updates.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260609130021.99899-1-cuiyunhui@bytedance.com?part=2

  reply	other threads:[~2026-06-09 13:16 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-09 13:00 [PATCH v3 0/3] riscv: support effective hardware PTE A/D updates Yunhui Cui
2026-06-09 13:00 ` [PATCH v3 1/3] dt-bindings: riscv: clarify Svadu boot-time behavior Yunhui Cui
2026-06-09 13:00 ` [PATCH v3 2/3] riscv: track effective hardware PTE A/D updating Yunhui Cui
2026-06-09 13:16   ` sashiko-bot [this message]
2026-06-09 13:00 ` [PATCH v3 3/3] riscv: preserve A/D and soft-dirty state across PTE updates Yunhui Cui

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