From: sashiko-bot@kernel.org
To: "Ciprian Costea" <ciprianmarian.costea@oss.nxp.com>
Cc: conor+dt@kernel.org, Frank.Li@kernel.org, robh@kernel.org,
imx@lists.linux.dev, devicetree@vger.kernel.org
Subject: Re: [PATCH v5 5/8] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk
Date: Tue, 09 Jun 2026 14:43:52 +0000 [thread overview]
Message-ID: <20260609144353.6BF781F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260609142954.1807421-6-ciprianmarian.costea@oss.nxp.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [Critical] Concurrent lockless modification of `skb_irq_queue` due to multiple independent IRQ handlers.
--
commit 715613f4f6a66b4bd5ff74d8a150e7fa13ca4aa1
Author: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk
This patch introduces the FLEXCAN_QUIRK_IRQ_BERR quirk for hardware that
has a dedicated interrupt line for bus errors and state changes. It adds
the flexcan_irq_esr() handler and updates IRQ enabling/disabling to
support the NXP S32N79 SoC.
> diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
> --- a/drivers/net/can/flexcan/flexcan-core.c
> +++ b/drivers/net/can/flexcan/flexcan-core.c
> @@ -1300,6 +1300,22 @@ static irqreturn_t flexcan_irq_boff(int irq, void *dev_id)
> return handled;
> }
>
> +/* Combined bus error and state change IRQ handler */
> +static irqreturn_t flexcan_irq_esr(int irq, void *dev_id)
> +{
> + struct net_device *dev = dev_id;
> + struct flexcan_priv *priv = netdev_priv(dev);
> + irqreturn_t handled;
> +
> + handled = flexcan_do_state(dev);
> + handled |= flexcan_do_berr(dev);
> +
> + if (handled)
> + can_rx_offload_irq_finish(&priv->offload);
> +
> + return handled;
> +}
> +
[ ... ]
> @@ -1902,6 +1919,13 @@ static int flexcan_open(struct net_device *dev)
> goto out_free_irq_boff;
> }
>
> + if (priv->devtype_data.quirks & FLEXCAN_QUIRK_IRQ_BERR) {
> + err = request_irq(priv->irq_err,
> + flexcan_irq_esr, IRQF_SHARED, dev->name, dev);
[Severity: Critical]
This isn't a bug introduced by this patch, but it expands a pre-existing
race condition to the S32N79 SoC by registering another concurrent hardware
IRQ handler.
Does registering multiple independent IRQ lines lead to concurrent lockless
modifications of the CAN rx-offload subsystem's skb_irq_queue?
If flexcan_irq_mb() and flexcan_irq_esr() trigger concurrently on different
CPUs:
CPU1 (flexcan_irq_mb)
flexcan_do_mb()
can_rx_offload_queue_timestamp()
__skb_queue_add_sort() <-- lockless push
CPU2 (flexcan_irq_esr)
flexcan_do_state()
can_rx_offload_queue_timestamp()
__skb_queue_add_sort() <-- concurrent lockless push
Or CPU1 could call can_rx_offload_irq_finish() (which splices the queue)
while CPU2 is pushing a new skb. Can this corrupt the doubly linked
skb_irq_queue pointers and cause kernel panics?
> + if (err)
> + goto out_free_irq_boff;
> + }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260609142954.1807421-1-ciprianmarian.costea@oss.nxp.com?part=5
next prev parent reply other threads:[~2026-06-09 14:43 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-09 14:29 [PATCH v5 0/8] can: flexcan: Add NXP S32N79 SoC support Ciprian Costea
2026-06-09 14:29 ` [PATCH v5 1/8] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms Ciprian Costea
2026-06-09 14:47 ` sashiko-bot
2026-06-09 14:29 ` [PATCH v5 2/8] can: flexcan: disable all IRQ lines in flexcan_chip_interrupts_enable() Ciprian Costea
2026-06-09 14:42 ` sashiko-bot
2026-06-09 14:29 ` [PATCH v5 3/8] can: flexcan: split rx/tx masks per mailbox IRQ line Ciprian Costea
2026-06-09 14:43 ` sashiko-bot
2026-06-09 14:29 ` [PATCH v5 4/8] dt-bindings: can: fsl,flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-06-09 14:29 ` [PATCH v5 5/8] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk Ciprian Costea
2026-06-09 14:43 ` sashiko-bot [this message]
2026-06-09 14:29 ` [PATCH v5 6/8] can: flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-06-09 14:41 ` sashiko-bot
2026-06-09 14:29 ` [PATCH v5 7/8] arm64: dts: s32n79: add FlexCAN nodes Ciprian Costea
2026-06-09 14:29 ` [PATCH v5 8/8] arm64: dts: s32n79: enable FlexCAN devices Ciprian Costea
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260609144353.6BF781F00893@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=Frank.Li@kernel.org \
--cc=ciprianmarian.costea@oss.nxp.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=imx@lists.linux.dev \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox