Re: [PATCH] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing `msi-map` device tree property in PCIe controller nodes.
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commit 0646a5585317fe9881a2b5cfe976f1ab1485cf3c
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes

This commit adds the PCIe controller and PHY nodes for the two PCIe instances
on the Eliza platform, and updates the GCC clock references to use the new
PHY nodes.

> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
> index 4a7a0ac40ce62..c4f0923710bbb 100644
> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi
> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
[ ... ]
> @@ -716,6 +716,361 @@ mmss_noc: interconnect@1780000 {
>  			#interconnect-cells = <2>;
>  		};
>  
> +		pcie0: pcie@1c00000 {
> +			device_type = "pci";
> +			compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550";
> +			reg = <0 0x01c00000 0 0x3000>,
[ ... ]
> +			operating-points-v2 = <&pcie0_opp_table>;
> +
> +			iommu-map = <0 &apps_smmu 0x1480 0x1>,
> +				    <0x100 &apps_smmu 0x1481 0x1>;
> +
> +			interrupt-map = <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 0 0 565 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 0 0 566 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 0 0 567 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			#interrupt-cells = <1>;
> +
> +			linux,pci-domain = <0>;

[Severity: High]
Should this node include the msi-map property?

Without an msi-map property to map PCIe Requester IDs to GIC ITS Device IDs,
the generic PCI device tree parsing code will fail to assign an MSI domain
to the PCIe bus. This prevents MSI and MSI-X operation for all downstream
devices, forcing a fallback to legacy INTx. The property is also required by
the qcom,pcie-common.yaml binding.

[ ... ]
> +		pcie1: pcie@1c08000 {
> +			device_type = "pci";
> +			compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550";
> +			reg = <0 0x01c08000 0 0x3000>,
[ ... ]
> +			operating-points-v2 = <&pcie1_opp_table>;
> +
> +			iommu-map = <0 &apps_smmu 0x1400 0x1>,
> +				    <0x100 &apps_smmu 0x1401 0x1>;
> +
> +			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			#interrupt-cells = <1>;
> +
> +			linux,pci-domain = <1>;

[Severity: High]
Is the msi-map property also missing for the pcie1 controller node?

As with pcie0 above, omitting the msi-map property prevents MSI/MSI-X
capabilities from being properly established for downstream devices.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260610-eliza_dt-v1-1-7bb72b75fc5b@oss.qualcomm.com?part=1