From: Krzysztof Kozlowski <krzk@kernel.org>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Conor Dooley <conor@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains
Date: Thu, 11 Jun 2026 11:28:15 +0200 [thread overview]
Message-ID: <20260611-serious-divergent-sidewinder-ec7ccb@quoll> (raw)
In-Reply-To: <0a57ab356e5f426e28ead373b809f88a63e55380.1781105151.git.geert+renesas@glider.be>
On Wed, Jun 10, 2026 at 05:29:20PM +0200, Geert Uytterhoeven wrote:
> On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
> Controller is located in a controllable power area.
Interesting... so to turn on L2 cache, OS would need to boot, setup
power domains handling, turn on power domain and then turn on L2 cache?
I understand that bootloader actually handles it, but I really doubt
that it is "controllable".
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-06-11 9:28 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-10 15:29 [PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains Geert Uytterhoeven
2026-06-11 9:28 ` Krzysztof Kozlowski [this message]
2026-06-11 9:37 ` Geert Uytterhoeven
2026-06-12 14:11 ` Rob Herring (Arm)
2026-06-12 15:45 ` Conor Dooley
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