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From: sashiko-bot@kernel.org
To: "Guodong Xu" <docular.xu@gmail.com>
Cc: conor+dt@kernel.org, kvm@vger.kernel.org, robh@kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v4 14/16] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
Date: Thu, 11 Jun 2026 20:32:42 +0000	[thread overview]
Message-ID: <20260611203242.D1AF41F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260611-rva23u64-hwprobe-v2-v4-14-3f01a2449488@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Profile detection incorrectly relies on monolithic superset bits (A, C, B) instead of granular component extensions, bypassing RVA23U64 on compliant hardware.
--

commit 1bae4d63d125b54f3683da372331e97613bffe86
Author: Guodong Xu <docular.xu@gmail.com>

riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection

This commit introduces a per-hart and host-wide bitmap for conformant ISA
profile bases, such as IMA and RVA23U64. It computes this at initialization
time by evaluating the resolved ISA bitmap against required extension sets.
This provides a cached profile state for subsequent consumers like hwprobe.

> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c

[ ... ]

> @@ -1322,3 +1325,90 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
> +/*
> + * Compute the set of profile bases (IMA, RVA23U64, ...) a hart
> + * conforms to, given its resolved ISA bitmap.
> + *
> + * If @isa_bitmap is NULL, the host ISA bitmap (the AND across all harts) is
> + * used.
> + */
> +static void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)
> +{
> +	const unsigned long *isa = isa_bitmap ? isa_bitmap : riscv_isa;
> +	DECLARE_BITMAP(ext_mask, RISCV_ISA_EXT_MAX) = { 0 };
> +
> +	/* IMA */
> +	__set_bit(RISCV_ISA_EXT_I, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_M, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_A, ext_mask);
> +
> +	if (!bitmap_subset(ext_mask, isa, RISCV_ISA_EXT_MAX))
> +		return;
> +
> +	set_bit(RISCV_ISA_BASE_IMA, bases);
> +
> +	/* RVA23U64 */
> +
> +	/* Supm with PMLEN=7 */
> +	if (!riscv_have_user_pmlen(7))
> +		return;
> +
> +	__set_bit(RISCV_ISA_EXT_F, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_D, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_C, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_B, ext_mask);

[Severity: High]
Does this logic correctly handle device trees that specify granular
extensions instead of monolithic supersets?

The kernel's riscv_resolve_isa() expands monolithic extensions into their
sub-extensions, but it does not synthesize monolithic extensions backwards
from their components.

If a compliant RVA23U64 platform specifies granular extensions like
zba, zbb, and zbs in its device tree rather than the legacy 'b' extension,
will this bitmap_subset() check fail because RISCV_ISA_EXT_B is not set?

This same pattern appears to affect the checks for A and C above as well.

> +	__set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260611-rva23u64-hwprobe-v2-v4-0-3f01a2449488@gmail.com?part=14

  reply	other threads:[~2026-06-11 20:32 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-11 20:12 [PATCH v4 00/16] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-06-11 20:12 ` [PATCH v4 01/16] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically Guodong Xu
2026-06-11 20:12 ` [PATCH v4 02/16] riscv: hwprobe.rst: Make indentation consistent Guodong Xu
2026-06-11 20:12 ` [PATCH v4 03/16] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP Guodong Xu
2026-06-11 20:12 ` [PATCH v4 04/16] riscv: Standardize extension capitalization Guodong Xu
2026-06-11 20:12 ` [PATCH v4 05/16] riscv: Add Zicclsm to cpufeature and hwprobe Guodong Xu
2026-06-11 20:12 ` [PATCH v4 06/16] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs " Guodong Xu
2026-06-11 20:12 ` [PATCH v4 07/16] riscv: Add B to hwcap " Guodong Xu
2026-06-11 20:12 ` [PATCH v4 08/16] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-06-11 20:12 ` [PATCH v4 09/16] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-06-11 20:50   ` Andrew Jones
2026-06-11 20:12 ` [PATCH v4 10/16] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-06-11 20:12 ` [PATCH v4 11/16] riscv: dts: spacemit: k1: " Guodong Xu
2026-06-11 20:12 ` [PATCH v4 12/16] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-06-11 20:12 ` [PATCH v4 13/16] riscv: Add a getter for user PMLEN support Guodong Xu
2026-06-11 20:12 ` [PATCH v4 14/16] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-06-11 20:32   ` sashiko-bot [this message]
2026-06-11 20:12 ` [PATCH v4 15/16] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-06-11 20:12 ` [PATCH v4 16/16] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-06-11 20:42   ` sashiko-bot

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