Re: [PATCH v6 3/5] iio: adc: versal-sysmon: add I2C driver

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The driver unconditionally registers an interrupt handler based on the Device Tree, which causes a panic on I2C systems because the I2C regmap backend cannot sleep in atomic context.
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commit adf35a1c0d89c3413cd1a863d9f01cfad15d4e03
Author: Salih Erim <salih.erim@amd.com>

iio: adc: versal-sysmon: add I2C driver

This commit adds an I2C transport driver for the Versal SysMon block. It
enables external masters to read voltage and temperature measurements through
the same register map used by the MMIO path, though events are not supported.

> diff --git a/drivers/iio/adc/versal-sysmon-i2c.c b/drivers/iio/adc/versal-sysmon-i2c.c
> new file mode 100644
> --- /dev/null
> +++ b/drivers/iio/adc/versal-sysmon-i2c.c

[ ... ]

> +static int sysmon_i2c_probe(struct i2c_client *client)
> +{
> +	struct device *dev = &client->dev;
> +	struct regmap *regmap;
> +
> +	regmap = devm_regmap_init(dev, NULL, client, &sysmon_i2c_regmap_config);
> +	if (IS_ERR(regmap))
> +		return PTR_ERR(regmap);
> +
> +	/* I2C has no IRQ connection; events are not supported */
> +	return sysmon_core_probe(dev, regmap);

[Severity: High]
If a misconfigured Device Tree provides an interrupts property for the I2C
node, will this unconditionally register a hardirq handler?

Looking at sysmon_core_probe() in versal-sysmon-core.c, it parses the IRQ
directly from the fwnode and sets up the interrupt if found:

    irq = fwnode_irq_get(dev_fwnode(dev), 0);
    ...
    if (irq > 0) {
        ...
        ret = sysmon_init_interrupt(sysmon, dev, indio_dev, irq);

If that interrupt fires, sysmon_iio_irq() attempts to take a spinlock and
perform a regmap_read():

    guard(spinlock)(&sysmon->irq_lock);

    if (regmap_read(sysmon->regmap, SYSMON_ISR, &isr) ||

Since the I2C regmap backend requires sleeping to perform I2C transfers,
won't executing this over I2C in a hardirq context cause a "scheduling while
atomic" panic?

Does the I2C transport need a mechanism to explicitly instruct the core probe
to bypass IRQ parsing?

> +}

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Sashiko AI review · https://sashiko.dev/#/patchset/20260611222738.2035062-1-salih.erim@amd.com?part=3