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Fri, 12 Jun 2026 02:58:00 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Fri, 12 Jun 2026 02:57:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Fri, 12 Jun 2026 02:57:58 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 998323F7040; Fri, 12 Jun 2026 02:57:56 -0700 (PDT) From: Geetha sowjanya To: , , , CC: , , , Subject: [PATCH v2 3/3] dt-bindings: perf: marvell: add CN20K TAD PMU support Date: Fri, 12 Jun 2026 15:27:46 +0530 Message-ID: <20260612095746.19679-4-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260612095746.19679-1-gakula@marvell.com> References: <20260612095746.19679-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Spam-Info: AW1haW4tMjYwNjEyMDA5MCBTYWx0ZWRfX79Tbtp8O1EPH /RTjvmPBrCemSS2BN1m2JnD+nxIXx+Iry3iADLUjuX/W+T6PfCMA88xy9u2EMx66n2AvJ+oz74x 0k4TOFKKKrLHQvi7bqOse+SO5mXZiaw= X-Authority-Analysis: v=2.4 cv=O6gJeh9W c=1 sm=1 tr=0 ts=6a2bd828 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=gEfo2CItAAAA:8 a=M5GUcnROAAAA:8 a=AeVSjtvhjGoncaazplIA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: nw9eWlCB1oYQ2K-mBnSTdd25psgSTRO0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEyMDA5MCBTYWx0ZWRfX8NuqNVdcdqKy zkULfZ3nA9WoZl6Odx1im34F5p+G/ladaH0SeYXmOGzm0bN9eiXzXqFjUulFVSq9Yjja0LM6bLT X2H46Rwme7HZi43PYq24gxd1joxE6kOP38IN5uc5VhOBnNMH7/xm38adMAEMm6KfcEAwnVfRS27 Iu4Asa4mbUNTOBEzSBKVsv4rrwSqndpo0lThml65uhTCLSpgT6vdaaKcommgH4sB3cu3AfjLj9G gdKsDJWk9Go/91ikkeTq2bLdEg3ot/u1BrOFWRKyxFC+0HBmZlzv0nnjM1EQ03N+VIyUTvRTuUF A038uCZpJo/p4N1d/3nwpThX/hN8Xc53sMAXzPVnmosR7taWMMnoeGdzjLnbKKGN5gNaFnKLPde 82Xqf56fMVejuQLooNSGi6KeI7Us1z55en9ASYLdzbOdUuWeiML0ozcI7pC7R19rt+haUzKTxGo zTmYAULC/5VGQzP6wXA== X-Proofpoint-ORIG-GUID: nw9eWlCB1oYQ2K-mBnSTdd25psgSTRO0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-12_01,2026-06-11_01,2025-10-01_01 Marvell CN20K SoCs integrate a Performance Monitoring Unit (PMU) associated with the LLC Tag-and-Data (TAD) blocks. The PMU provides hardware counters to monitor cache traffic and performance events via a dedicated MMIO region. The CN20K LLC-TAD PMU is largely similar to CN10K, but differs in the layout of PFC/PRF register offsets relative to each TAD base. These offsets are derived from the compatible string in the driver and are not described through Devicetree properties. Because of this, using "marvell,cn10k-tad-pmu" as a fallback for CN20K would result in incorrect register programming. Therefore, add a separate compatible string: "marvell,cn20k-tad-pmu" Update the binding to document CN20K alongside CN10K. Signed-off-by: Geetha sowjanya --- Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml | 17 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml index 362142252667..d11121a1e2c9 100644 --- a/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml @@ -4,23 +4,32 @@ $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Marvell CN10K LLC-TAD performance monitor +title: Marvell CN10K / CN20K LLC-TAD performance monitor maintainers: - Bhaskara Budiredla + - Geetha sowjanya description: | - The Tag-and-Data units (TADs) maintain coherence and contain CN10K - shared on-chip last level cache (LLC). The tad pmu measures the - performance of last-level cache. Each tad pmu supports up to eight - counters. + The Tag-and-Data units (TADs) maintain coherence and contain the + shared on-chip last level cache (LLC) on Marvell CN10K and CN20K SoCs. + The TAD PMU measures last-level cache performance. Each TAD PMU + supports up to eight counters. - The DT setup comprises of number of tad blocks, the sizes of pmu - regions, tad blocks and overall base address of the HW. + The DT setup describes the number of TAD blocks, the sizes of PMU + regions and TAD pages, and the overall MMIO base of the hardware. + + marvell,cn20k-tad-pmu is not a compatible fallback for + marvell,cn10k-tad-pmu (and vice versa): the driver selects different + PFC/PRF MMIO offsets from the compatible string, and those offsets are + not described by separate DT properties today. properties: compatible: - const: marvell,cn10k-tad-pmu + items: + - enum: + - marvell,cn10k-tad-pmu + - marvell,cn20k-tad-pmu reg: maxItems: 1 -- 2.25.1