Re: [PATCH 4/5] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] Missing Required Property in UART node `serial_0`
- [Medium] Device Tree Topology Error: `cluster1` skips `core2`
- [Low] Device Tree Binding Violation in `timer` node interrupts
- [Low] DT Binding Violation: Missing `-gpio-bank` suffix on GPIO bank nodes
- [Low] Device Tree Syntax Error: `gic` node defines `#size-cells = <1>` without `#address-cells = <1>`
--

commit fb7d1034f06462e074dc2aa5a08df68787706d6c
Author: Alim Akhtar <alim.akhtar@samsung.com>

arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
    
Add initial devicetree support for Samsung smdk board using
Exynos8855 SoC.

> diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> new file mode 100644
> index 0000000000000..f5d30fd299b62
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> @@ -0,0 +1,581 @@
[ ... ]
> +&pinctrl_alive {
> +	gpa0: gpa0 {
> +		gpio-controller;
> +		#gpio-cells = <2>;

[Severity: Low]
Does this missing suffix violate the Exynos pinctrl dt-binding schema?

Nodes such as gpa0 and gpm0 appear to be missing the required
-gpio-bank suffix, which the schema expects to match the pattern:

    ^[a-z0-9-]+-gpio-bank$

Without this suffix, the nodes will fail DT schema validation, even though
the Linux pinctrl driver will still parse them by iterating over child nodes.

> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
[ ... ]
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
> new file mode 100644
> index 0000000000000..cffa40b6bb986
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
> @@ -0,0 +1,214 @@
[ ... ]
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu4>;
> +				};
> +				core1 {
> +					cpu = <&cpu5>;
> +				};
> +				core3 {
> +					cpu = <&cpu6>;
> +				};

[Severity: Medium]
Is it intentional to skip core2 in the cpu-map topology array?

The cluster1 node defines core0, core1, and core3, completely skipping
core2. Device tree topology indices are generally expected to be contiguous.

Skipping core2 might misrepresent the actual hardware topology and confuse
kernel topology parsers or the task scheduler.

> +			};
> +
> +			cluster2 {
[ ... ]
> +		gic: interrupt-controller@10200000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <4>;
> +			#address-cells = <0>;
> +			#size-cells = <1>;

[Severity: Low]
Is this #size-cells assignment a device tree syntax error?

The gic node explicitly specifies #address-cells = <0>, but sets
#size-cells = <1>. In Device Tree syntax, if #address-cells is 0, the node's
children cannot have sizes, so #size-cells must also be 0 or omitted.

This mismatch will trigger the avoid_unnecessary_addr_size dtc compiler
warning.

> +			reg = <0x10200000 0x10000>,
> +			      <0x10240000 0x100000>;
[ ... ]
> +		serial_0: serial@15500000 {
> +			compatible = "samsung,exynos850-uart";
> +			reg = <0x15500000 0x100>;
> +			interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&uart0_bus>;
> +		};

[Severity: High]
Does this node need clocks and clock-names properties?

The samsung_tty driver unconditionally requests the uart clock during its
probe() function via devm_clk_get(). Without these properties, the driver's
probe will fail with -ENOENT and abort.

Since serial_0 is set as the stdout-path in the board DTS, this failure
would result in a non-functional serial console.

> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
> +		interrupts =
> +		     <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,

[Severity: Low]
Are these interrupt definitions violating the GICv3 device tree bindings?

The timer node defines its GICv3 PPI interrupts using the
GIC_CPU_MASK_SIMPLE(8) macro and IRQ_TYPE_LEVEL_LOW.

Under GICv3 device tree bindings, the 3rd cell must only encode trigger type
and level flags; embedding CPU affinity masks violates the schema.
Additionally, GIC device tree bindings standardly expect
IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.

This will trigger dtbs_check validation warnings, though the Linux GICv3
driver safely masks out the unsupported bits at runtime.

> +		     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
> +		     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
> +		     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260612163020.411761-1-alim.akhtar@samsung.com?part=4