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Fri, 12 Jun 2026 23:58:40 -0700 (PDT) From: MidG971 To: tomeu@tomeuvizoso.net, ogabbay@kernel.org, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, xxm@rock-chips.com, chaoyi.chen@rock-chips.com, finley.xiao@rock-chips.com, diederik@cknow-tech.com, jonas@kwiboo.se, Midgy BALON Subject: [RFC PATCH v4 7/9] arm64: dts: rockchip: rk356x: Add the NPU and its IOMMU Date: Sat, 13 Jun 2026 09:01:14 +0200 Message-Id: <20260613070116.438906-8-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260613070116.438906-1-midgy971@gmail.com> References: <20260613070116.438906-1-midgy971@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Midgy BALON The RK3568 has an NVDLA-derived NPU at fde40000 with its own IOMMU at fde4b000. Add both nodes (disabled by default) and the NPU power-domain child under the PMU power-controller, and point rockchip,pmu at the PMU syscon that controls the NPU NoC bus-idle. Besides the SCMI compute clock, assign the CRU CLK_NPU so the NPU AXI bus clock comes up at 200 MHz rather than the 12 MHz boot default. The power-domain deliberately carries no pm_qos: qos_npu sits behind the NPU NoC, which is gated until the NPU is brought up, so a genpd power-off QoS save would fault reading it. Signed-off-by: Midgy BALON --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 64bdd8b7754b5..313db59c1aed8 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -512,6 +512,13 @@ power-domain@RK3568_PD_GPU { #power-domain-cells = <0>; }; + pd_npu: power-domain@RK3568_PD_NPU { + reg = ; + clocks = <&cru ACLK_NPU_PRE>, + <&cru HCLK_NPU_PRE>; + #power-domain-cells = <0>; + }; + /* These power domains are grouped by VD_LOGIC */ power-domain@RK3568_PD_VI { reg = ; @@ -572,6 +579,37 @@ power-domain@RK3568_PD_RKVENC { }; }; + rknn_core_0: npu@fde40000 { + compatible = "rockchip,rk3568-rknn-core"; + reg = <0x0 0xfde40000 0x0 0x1000>, + <0x0 0xfde41000 0x0 0x1000>, + <0x0 0xfde43000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = ; + clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_PRE>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru CLK_NPU>; + assigned-clock-rates = <200000000>, <600000000>; + resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3568_PD_NPU>; + rockchip,pmu = <&pmu>; + iommus = <&rknn_mmu_0>; + status = "disabled"; + }; + + rknn_mmu_0: iommu@fde4b000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xfde4b000 0x0 0x40>; + interrupts = ; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>; + power-domains = <&power RK3568_PD_NPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + gpu: gpu@fde60000 { compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; reg = <0x0 0xfde60000 0x0 0x4000>; -- 2.39.5