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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3081ddaf69asm14295300eec.0.2026.06.14.22.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jun 2026 22:49:17 -0700 (PDT) From: Joey Lu To: Vinod Koul , Neil Armstrong Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Catalin Marinas , Jacky Huang , Shan-Chun Hung , Hui-Ping Chen , Joey Lu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 0/3] phy: nuvoton: extend MA35D1 USB2 PHY driver for dual-port OTG support Date: Mon, 15 Jun 2026 13:49:08 +0800 Message-ID: <20260615054911.48821-1-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MA35D1 SoC has two USB PHY ports managed by a shared hardware block: - PHY0 (USB0): OTG port shared between the DWC2 gadget controller and the EHCI0/OHCI0 host controllers. A hardware mux automatically routes USB0 signals to the correct controller based on the USB ID pin. - PHY1 (USB1): dedicated host-only port for EHCI1/OHCI1. A previous series [1] added a separate phy-ma35d1-otg.c driver for this. Following reviewer suggestion to reuse the existing phy-ma35d1-usb2.c driver rather than introduce a new one, that series has been dropped and this series instead extends the existing driver. Changes in this series: Patch 1 updates the nuvoton,ma35d1-usb2-phy binding: the PHY node becomes a child of the syscon node (reg = <0x60 0x14>), nuvoton,sys phandle and clocks are removed, and #phy-cells changes from 0 to 1 for per-port selection. Optional nuvoton,rcalcode and nuvoton,oc-active-high properties are added. Patch 2 updates the MA35D1 DTS: sys gains simple-mfd, usb-phy@60 is added as a syscon child, and DWC2/EHCI0/EHCI1/OHCI0/OHCI1 nodes are added. Board files enable the nodes and add HSUSB pinctrl. Patch 3 extends phy-ma35d1-usb2.c: a loop creates two struct phy objects; a unified .init handles both ports with parametric register macros; clock management is removed (each controller gates its own clock); a read-only USB role switch is registered for PHY0 reporting the USB ID pin via PWRONOTP[16]. Link: [1] https://lore.kernel.org/linux-phy/20260604101220.1092822-1-a0987203069@gmail.com/T/#t Joey Lu (3): dt-bindings: phy: nuvoton,ma35d1-usb2-phy: extend for dual-port OTG support arm64: dts: nuvoton: ma35d1: add USB controllers and dual-port PHY node phy: nuvoton: phy-ma35d1-usb2: extend to dual-port with OTG support .../bindings/phy/nuvoton,ma35d1-usb2-phy.yaml | 67 +++-- .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 36 +++ .../boot/dts/nuvoton/ma35d1-som-256m.dts | 36 +++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 68 ++++- drivers/phy/nuvoton/phy-ma35d1-usb2.c | 263 +++++++++++++----- 5 files changed, 378 insertions(+), 92 deletions(-) base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731 -- 2.43.0