Re: [PATCH v2 4/4] iio: dac: ad3530r: Add support for AD3532R/AD3532

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `AD3532R_MAX_REG_ADDR` macro is off by one byte, which breaks read and write operations for the highest channel (channel 15).
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commit 26c7d468b3bc4ece87a824dffd3ce6a739dc9fcd
Author: Kim Seer Paller <kimseer.paller@analog.com>

iio: dac: ad3530r: Add support for AD3532R/AD3532

The AD3532R/AD3532 is a 16-channel, 16-bit voltage output DAC with a
dual-bank register architecture. This patch adds AD3532R-specific register
definitions, channel specs, per-bank register arrays, and per-chip
regmap configurations.

> diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c
> --- a/drivers/iio/dac/ad3530r.c
> +++ b/drivers/iio/dac/ad3530r.c
> @@ -39,6 +40,22 @@

[ ... ]

> +#define AD3532R_SW_LDAC_TRIG_0			0x10E5
> +#define AD3532R_SW_LDAC_TRIG_1			0x30E5
> +#define AD3532R_INPUT_CH_0			0x10EB
> +#define AD3532R_INPUT_CH_1			0x30EB
> +#define AD3532R_MAX_REG_ADDR			0x30F9

[Severity: High]
Will this maximum register address break accesses for channel 15?

Since ad3532r_input_ch_reg(15) correctly returns the base register address
0x30F9, and val_bits is 8 for this 16-bit DAC, accessing the channel requires
reading or writing 2 bytes (addresses 0x30F9 and 0x30FA).

If max_register is restrictively defined as 0x30F9, the regmap subsystem's
bounds check will reject the access to 0x30FA and return -EINVAL during
regmap_bulk_read() or regmap_bulk_write() operations.

It looks like this might be a copy of a pre-existing bug in the driver, as
AD3530R_MAX_REG_ADDR is set to 0xF9, which would similarly break channel 7
on the AD3530R.

> +
>  #define AD3530R_SLD_TRIG_A			BIT(7)

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Sashiko AI review · https://sashiko.dev/#/patchset/20260615-iio-ad3532r-support-v2-0-84a0af8b83fa@analog.com?part=4