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From: sashiko-bot@kernel.org
To: "Joey Lu" <a0987203069@gmail.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org,
	dri-devel@lists.freedesktop.org, conor+dt@kernel.org
Subject: Re: [PATCH v4 1/6] dt-bindings: display: verisilicon,dc: generalize for single-output variants
Date: Mon, 15 Jun 2026 06:55:58 +0000	[thread overview]
Message-ID: <20260615065558.8E3E21F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260615065003.76661-2-a0987203069@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The top-level `clock-names` property enforces a strict positional sequence (`core`, `axi`, `ahb`, `pix0`, `pix1`) that conflicts with the `nuvoton,ma35d1-dcu` variant, causing valid device trees to fail schema validation.
--

commit 644d6513333f2ad52d35609ed1c0190fdeaa8192
Author: Joey Lu <a0987203069@gmail.com>

dt-bindings: display: verisilicon,dc: generalize for single-output variants

This commit generalizes the verisilicon,dc schema to support single-output
variants. It extracts variant-specific constraints into allOf/if blocks and
adds support for the Nuvoton MA35D1 SoC.

> diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
[ ... ]
>    clock-names:
> +    minItems: 2
> +    maxItems: 5
>      items:
>        - const: core
>        - const: axi
>        - const: ahb
>        - const: pix0
>        - const: pix1
[ ... ]
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: nuvoton,ma35d1-dcu
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 2
> +          maxItems: 2
> +          items:
> +            - description: DC Core clock
> +            - description: Pixel clock of output 0
> +
> +        clock-names:
> +          minItems: 2
> +          maxItems: 2

[Severity: Medium]
Will this cause validation failures for valid device trees?

The top-level clock-names defines a strict positional sequence where the 
second item must be "axi". However, the clocks definition for the 
nuvoton,ma35d1-dcu variant indicates it uses "core" and "pix0".

Since the variant's clock-names block doesn't redefine the items array, won't
dt-schema evaluate "pix0" against the inherited "axi" constraint at index 1 
and fail?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260615065003.76661-1-a0987203069@gmail.com?part=1

  reply	other threads:[~2026-06-15  6:55 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-15  6:49 [PATCH v4 0/6] drm/verisilicon: add Nuvoton MA35D1 DCU Lite support Joey Lu
2026-06-15  6:49 ` [PATCH v4 1/6] dt-bindings: display: verisilicon,dc: generalize for single-output variants Joey Lu
2026-06-15  6:55   ` sashiko-bot [this message]
2026-06-15  8:19   ` [PATCH v4 1/6] dt-bindings: display: verisilicon, dc: " Icenowy Zheng
2026-06-15  6:49 ` [PATCH v4 2/6] drm/verisilicon: add register-level macros for DC8000 Joey Lu
2026-06-15  8:24   ` Icenowy Zheng
2026-06-15  6:50 ` [PATCH v4 3/6] drm/verisilicon: introduce per-variant hardware ops table Joey Lu
2026-06-15  7:02   ` sashiko-bot
2026-06-15  8:37   ` Icenowy Zheng
2026-06-15  6:50 ` [PATCH v4 4/6] drm/verisilicon: add DC8000 (DCUltraLite) display controller support Joey Lu
2026-06-15  8:51   ` Icenowy Zheng
2026-06-15  9:04   ` sashiko-bot
2026-06-15  6:50 ` [PATCH v4 5/6] drm/verisilicon: add DCUltraLite chip identity to HWDB Joey Lu
2026-06-15  6:59   ` sashiko-bot
2026-06-15  8:57   ` Icenowy Zheng
2026-06-15  6:50 ` [PATCH v4 6/6] drm/verisilicon: extend Kconfig to support ARCH_MA35 platforms Joey Lu
2026-06-15  8:58   ` Icenowy Zheng

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