Re: [PATCH v3 1/5] clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The documentation for `input_fref` explicitly states it should be in MHz, but the implementation assumes and requires Hz.
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commit bcb3fbb3f1de21bfd1e1a632fe1e124e9c03de3b
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations

This commit introduces a per-SoC PLL reference input frequency parameter to
the rzv2h_pll_limits struct. It updates the PLL calculation logic to use
this dynamically provided reference frequency instead of a hardcoded 24MHz
constant, falling back to 24MHz if the field is not initialized.

> diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
> index f6c47fb89bca5..513f8283c4796 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
[ ... ]
> @@ -237,6 +236,7 @@ struct rzv2h_plldsi_div_clk {
>  bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
>  			struct rzv2h_pll_pars *pars, u64 freq_millihz)
>  {
> +	unsigned long input_fref = limits->input_fref ?: (24 * MEGA);

[ ... ]

> diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h
> index c360df9fa735c..94ee70b20b44c 100644
> --- a/include/linux/clk/renesas.h
> +++ b/include/linux/clk/renesas.h
> @@ -53,6 +53,9 @@ static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { }
>   * various parameters used to configure a PLL. These limits ensure
>   * the PLL operates within valid and stable ranges.
>   *
> + * @input_fref: Reference input frequency to the PLL (in MHz). If set
> + * to 0, a default value of 24MHz is used.

[Severity: Low]
The documentation here states that the frequency should be provided in MHz,
but the implementation in rzv2h_get_pll_pars() expects Hz, as it falls back
to (24 * MEGA) and doesn't scale input_fref.

If a developer configures a new SoC and sets .input_fref = 48 as documented,
will it be evaluated as 48 Hz instead of 48 MHz and cause the PLL limit checks
to fail? Should the kernel-doc be updated to request the frequency in Hz?

>   *
>   * @fout: Output frequency range (in MHz)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260615104845.4122868-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=1