Re: [PATCH v3 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The L1 data cache size for the Cortex-A520 cores (cpu0 and cpu1) is incorrectly set to 64KB (`<65536>`) instead of 32KB (`<32768>`).
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commit e69e8fc4f3866077641d02b02b7f11554b632507
Author: Neil Armstrong <neil.armstrong@linaro.org>

arm64: dts: qcom: sm8650: add CPU cache size properties

This commit adds L1, L2, and L3 cache size and line size properties to the
CPU and cache nodes in the sm8650 device tree. It splits the unified L1
cache properties into instruction and data cache sizes based on clidr_el1.

> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index e8e43ddc3032a..090a4739ebc1d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -75,6 +75,11 @@ cpu0: cpu@0 {
>  			compatible = "arm,cortex-a520";
>  			reg = <0 0>;
>  
> +			i-cache-size = <65536>;
> +			i-cache-line-size = <64>;
> +			d-cache-size = <65536>;

[Severity: Medium]
Is the d-cache-size for the Cortex-A520 correct here? 

According to the ARM Cortex-A520 Technical Reference Manual, the L1 data cache
is strictly fixed at 32KB (<32768>), even though the instruction cache can be
configured to 32KB or 64KB. 

This misrepresentation of the hardware topology could potentially lead to
suboptimal scheduling decisions or misguide userspace optimization algorithms.

> +			d-cache-line-size = <64>;
> +
>  			clocks = <&cpufreq_hw 0>;

[ ... ]

> @@ -117,6 +126,11 @@ cpu1: cpu@100 {
>  			compatible = "arm,cortex-a520";
>  			reg = <0 0x100>;
>  
> +			i-cache-size = <65536>;
> +			i-cache-line-size = <64>;
> +			d-cache-size = <65536>;

[Severity: Medium]
Does this node also need to be updated to <32768> for the 32KB fixed L1 data
cache on the Cortex-A520, similar to cpu0?

> +			d-cache-line-size = <64>;
> +
>  			clocks = <&cpufreq_hw 0>;

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Sashiko AI review · https://sashiko.dev/#/patchset/20260615-topic-sm8650-upstream-cpu-props-v3-0-eeb6e9fa7581@linaro.org?part=2