From: sashiko-bot@kernel.org
To: "Neil Armstrong" <neil.armstrong@linaro.org>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH RFC v3 1/6] arm64: dts: qcom: add PMIC5 Gen3 macros for channel numbers
Date: Mon, 15 Jun 2026 17:07:55 +0000 [thread overview]
Message-ID: <20260615170756.0BD611F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260615-topic-sm8x50-adc5-gen3-v3-1-216a2b5ccb85@linaro.org>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] Incorrect include guards ('ACD5' instead of 'ADC5') in the PMIC specific ADC headers.
- [Low] Leading space before SPDX-License-Identifier comment.
--
commit 3eda1039cbb8425b3c3af45f1320fc946f6b44cd
Author: Neil Armstrong <neil.armstrong@linaro.org>
arm64: dts: qcom: add PMIC5 Gen3 macros for channel numbers
This commit adds PMIC5 Gen3 macros to calculate ADC channel numbers based on
SPMI bus numbers and sensor configurations. It moves the macro definitions from
dt-bindings to local includes for better DT source readability.
Link: https://lore.kernel.org/all/20250826083657.4005727-4-jishnu.prakash@oss.qualcomm.com/
> diff --git a/arch/arm64/boot/dts/qcom/qcom,adc5-gen3-channels.h b/arch/arm64/boot/dts/qcom/qcom,adc5-gen3-channels.h
> new file mode 100644
> index 0000000000000..a8aac9ae6f404
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcom,adc5-gen3-channels.h
> @@ -0,0 +1,88 @@
> + /* SPDX-License-Identifier: GPL-2.0 */
[Severity: Low]
This isn't a bug, but there is a leading space before the SPDX identifier on
the first line. Could this be removed to ensure automated scanners and
checkpatch.pl find the tag where they expect it?
[ ... ]
> diff --git a/arch/arm64/boot/dts/qcom/qcom,pm8550-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom,pm8550-adc5-gen3.h
> new file mode 100644
> index 0000000000000..2a6338812d4e9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcom,pm8550-adc5-gen3.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _QCOM_PM8550_ACD5_GEN3_H
> +#define _QCOM_PM8550_ACD5_GEN3_H
[Severity: Low]
This isn't a bug, but should these header guards use ADC5 instead of ACD5?
[ ... ]
> diff --git a/arch/arm64/boot/dts/qcom/qcom,pm8550b-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom,pm8550b-adc5-gen3.h
> new file mode 100644
> index 0000000000000..312daa846f798
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcom,pm8550b-adc5-gen3.h
> @@ -0,0 +1,85 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _QCOM_PM8550B_ACD5_GEN3_H
> +#define _QCOM_PM8550B_ACD5_GEN3_H
[Severity: Low]
This isn't a bug, but there is also a typo here using ACD5 instead of ADC5
in the include guards.
[ ... ]
> diff --git a/arch/arm64/boot/dts/qcom/qcom,pm8550vx-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom,pm8550vx-adc5-gen3.h
> new file mode 100644
> index 0000000000000..7a261a7a9cb08
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcom,pm8550vx-adc5-gen3.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _QCOM_PM8550VX_ACD5_GEN3_H
> +#define _QCOM_PM8550VX_ACD5_GEN3_H
[Severity: Low]
This isn't a bug, but this guard also has the ACD5 typo.
[ ... ]
> diff --git a/arch/arm64/boot/dts/qcom/qcom,pmk8550-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom,pmk8550-adc5-gen3.h
> new file mode 100644
> index 0000000000000..60b3b9c60d4e2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcom,pmk8550-adc5-gen3.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _QCOM_PMK8550_ACD5_GEN3_H
> +#define _QCOM_PMK8550_ACD5_GEN3_H
[Severity: Low]
This isn't a bug, but this guard has the same ACD5 typo as well.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260615-topic-sm8x50-adc5-gen3-v3-0-216a2b5ccb85@linaro.org?part=1
next prev parent reply other threads:[~2026-06-15 17:07 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-15 17:00 [PATCH RFC v3 0/6] arm64: dts: qcom: sm8[56]50: add PMIC5 Gen3 ADC channels Neil Armstrong
2026-06-15 17:00 ` [PATCH RFC v3 1/6] arm64: dts: qcom: add PMIC5 Gen3 macros for channel numbers Neil Armstrong
2026-06-15 17:07 ` sashiko-bot [this message]
2026-06-15 23:58 ` Dmitry Baryshkov
2026-06-15 17:00 ` [PATCH RFC v3 2/6] arm64: dts: qcom: pmk8550: add VADC node Neil Armstrong
2026-06-15 23:58 ` Dmitry Baryshkov
2026-06-15 17:00 ` [PATCH RFC v3 3/6] arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes Neil Armstrong
2026-06-15 17:15 ` sashiko-bot
2026-06-15 23:59 ` Dmitry Baryshkov
2026-06-15 17:00 ` [PATCH RFC v3 4/6] arm64: dts: qcom: sm8550-hdk: " Neil Armstrong
2026-06-16 0:00 ` Dmitry Baryshkov
2026-06-15 17:00 ` [PATCH RFC v3 5/6] arm64: dts: qcom: sm8650-qrd: " Neil Armstrong
2026-06-15 17:11 ` sashiko-bot
2026-06-15 17:00 ` [PATCH RFC v3 6/6] arm64: dts: qcom: sm8650-hdk: " Neil Armstrong
2026-06-15 17:15 ` sashiko-bot
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