From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from twmbx01.aspeedtech.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7640B3C13FD; Tue, 16 Jun 2026 03:30:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781580613; cv=none; b=p7Jdx780SEJ3s7dBOxLwRf7yBuunXISy3UthF1T/X2Gb+D8phwyQRozmX5KitxhTKh6kAF3pBNToQWcqjoPt1gLY9DB4e6kaE4MRpujP4KEOnyB1DhH0c5MkEcZpOpEWYX60cWWVhuDWYBSKdYkCbz2dL7luIdG2ZLUIIMh4RYw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781580613; c=relaxed/simple; bh=3g5Xwg8h1zZKhm3yigBW7k/XgEh1YvhsBXpVJn3jjYc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=PodfYqILzksl0hxMMP6pprG8o9qzxNrWyIRk1YCec3g8igO04O2O2zRJ4pwXN7gPzBcHtPEoV/2QnrZfIknYrG1cZ371AFK1GMlPHFd2voN3gGUiNU7L0Kx4wgvC6Pgd2mRwZd6oVHX11y2Eft/KcVVQN8NoyTuK3xynWD5f+7c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 16 Jun 2026 11:30:02 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 16 Jun 2026 11:30:02 +0800 From: Billy Tsai Date: Tue, 16 Jun 2026 11:30:02 +0800 Subject: [PATCH 2/2] pinctrl: aspeed: Split TRST out of the AST2700 SoC1 JTAGM1 group Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260616-pinctrl-fix-v1-2-621036e45c7c@aspeedtech.com> References: <20260616-pinctrl-fix-v1-0-621036e45c7c@aspeedtech.com> In-Reply-To: <20260616-pinctrl-fix-v1-0-621036e45c7c@aspeedtech.com> To: Andrew Jeffery , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley CC: , , , , , , "Billy Tsai" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781580602; l=1914; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=3g5Xwg8h1zZKhm3yigBW7k/XgEh1YvhsBXpVJn3jjYc=; b=8/rgiPAyR99n1WV2vAnALgdaOrGtS/4Pyejknog3mNZ6wbRX5G6acnNUpKvpkyOieYdOYck9k mkV47AQIGOhCU3adl3tEKUMaH7IRepbeciaAkhCja6uYFwxUU0eA1qV X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= The JTAGM1 group includes the D12 ball carrying the TRST signal, but TRST is optional for a JTAG master and the ball may be needed for other functions on designs that do not wire it. With TRST embedded in the group, such designs cannot use the JTAG master at all. Move D12 into a new JTAGM1TRST group under the same JTAGM1 function so TRST is muxed only when a board requests it. Boards that do use TRST now need to select both the JTAGM1 and JTAGM1TRST groups. Signed-off-by: Billy Tsai --- drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c index 50027d69c342..f8b4066699ce 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c @@ -1018,7 +1018,8 @@ PIN_GROUP(I3C6, AA22, AB20); PIN_GROUP(I3C7, AF18, AE19); PIN_GROUP(I3C8, AD20, AC20); PIN_GROUP(I3C9, AA21, AB21); -PIN_GROUP(JTAGM1, D12, F10, E11, F11, F13); +PIN_GROUP(JTAGM1, F10, E11, F11, F13); +PIN_GROUP(JTAGM1TRST, D12); PIN_GROUP(LPC0, AF26, AF25, B16, D14, B15, B14, C17, B13, E14, C15); PIN_GROUP(LPC1, C16, C14, C11, D9, F14, D10, C12, C13, AE16, AE17); PIN_GROUP(LTPI, U25, U26, Y26, AA24); @@ -1263,6 +1264,7 @@ static const struct pingroup aspeed_g7_soc1_groups[] = { GROUP(I3C8), GROUP(I3C9), GROUP(JTAGM1), + GROUP(JTAGM1TRST), GROUP(LPC0), GROUP(LPC1), GROUP(LTPI), @@ -1528,7 +1530,7 @@ static const struct aspeed_g7_soc1_function aspeed_g7_soc1_functions[] = { FUNC(I3C7, (1), "I3C7"), FUNC(I3C8, (1), "I3C8"), FUNC(I3C9, (1), "I3C9"), - FUNC(JTAGM1, (1), "JTAGM1"), + FUNC(JTAGM1, (1, 1), "JTAGM1", "JTAGM1TRST"), FUNC(LPC0, (2), "LPC0"), FUNC(LPC1, (2), "LPC1"), FUNC(LTPI, (2), "LTPI"), -- 2.34.1