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Tue, 16 Jun 2026 13:26:51 -0700 (PDT) Received: from [192.168.0.2] ([197.250.51.220]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49230a458f2sm89987005e9.3.2026.06.16.13.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 13:26:50 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Subject: [PATCH RFC v4 00/12] ZTE zx297520v3 clock bindings and driver Date: Tue, 16 Jun 2026 23:26:20 +0300 Message-Id: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/2WOQU7DMBBFrxJ5jZE9YydxV0hIHIAtYmE749Zq0 4AdokKVu2MZpEaw/DPz3vwry5QiZbZrrizREnOcziWou4b5gz3vicehZAYCWqGl4F8XMP505EB qQEMoofesXL8lCvFSTS/s+emRvf4ME71/FOv8u3E2E/fTOMZ513hJ3gGaYFHpVoOxCKA1ahN81 7vWkDNDr7rqOsQ8T+mzNl1klf0rtUguOElnfQiBTNs97EcbT/flYXUssOXkjYPCgQmCBo9CBP2 Xww0H5sZh4XwXSCuy2Pdhy63r+g3mrePpXwEAAA== X-Change-ID: 20260510-zx29clk-2e4d39e3128c To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3793; i=stefandoesinger@gmail.com; h=from:subject:message-id; bh=FwO80H1E3JHTygfTphnHg7nPuRMZdLoWNR8BX9Qlzrk=; b=owEBiQJ2/ZANAwAIAT0TvMhUTxoiAcsmYgBqMbGA2Nqb6P7bZNY0Jn4Ahgvm54BiflHnww1Wp u3KXRrPtbCJAk8EAAEIADkWIQRDFvS2qgVbJ5UyXWw9E7zIVE8aIgUCajGxgBsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDIACgkQPRO8yFRPGiKA+hAAnx40hgB9SBYrpop0r6jTAhXwWFB+/nn 8O5iuk7DJYzsn3lFHR+tQsG/3cq8O7tocyhW4ubq6jhNbAzdzsYG6+XgURtNbokwpiShr/YAiDb 4oQ1NC8EXwXA7LgrmX2yZdOmbAyxuRhzMRybynIIdF1njxSpkjG00NV2Zd0yKyQcNzuD2F2YAym 0FVMdmgtHajdER14GjV7j/lVTxhLlYSWAywYjzo12eOhe46yC2wEpvYNDXwvgnxqp/pWsMHS1UC +nK7V4n9pzLusWq0KIbO/QhI5e5ZqmigRzmls9mRjJvpa51E/tzbJCnxJm3JWpHw/ORPl6iMw5O gg4JE/Gq2lO3gfmdpPlFhXZ5BTAJWVB1bhiSj1rX+qok978+gl79sn34X1UFOI7leRg4W+bARP7 UCH19kVRvyS57uxdSj979jBaGnUBk7W9m8YvESecdVtlcvRK47vAR/4QH330wX8kgNkxV9SfAlg Uk6pDKy1JQ+Jvq7EGbEIDjbjIPOfukvF4YJm5vu8z+QbLOMA0pimFP9kDsfHb6JDPEW1m83p9HU h+eW2BFnEfs75ZDUTn1jsbm/hhRvEGoCqKcq7hvHELRO3NtnT+5Pl/uJgIqMTepp4EDDqeIkjKK eP6OcLPboHD1sgSiQp35Tdl+pAfF0drGakTpXhQvSlYivxx4SD3k= X-Developer-Key: i=stefandoesinger@gmail.com; a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 Hi, I am sending version 4 of my zx297520v3 clock patch. The major change is using regmaps rather than raw mmio to access the clocks and moving reset handling into its own aux bus driver. I think the list of clocks in my driver is fairly complete; It is certainly a lot better than what the downstream ZTE drivers have. I deduced a lot of it by trial and error. I am sure there are some clocks missing that will need to be added to the binding later. Afaiu adding clocks is not an issue, but removing or reordering them is an ABI break. I expect Sashiko to find a lot of slopiness mistakes, so I kept the [RFC] tag for this submission. Signed-off-by: Stefan Dösinger --- Changes in v4: *) Use syscon and regmap instead of raw IO *) Move reset to its own driver on the aux bus, but keep reset and clk in the same binding as it matches the way the hardware works *) Go back to having matrixclk in its own device because syscon deals poorly with multi io reg devices. List all PLL outputs from topclk as inputs to matrixclk *) Some more hardware research: Figure out the parents of the 4 possible GPIO clock outputs and declare them in the driver. They are unused on the hardware I have, but they show that all PLLs can be used. - Link to v3: https://lore.kernel.org/r/20260529-zx29clk-v3-0-c7fe54ea388f@gmail.com Changes in v3: Model top and matrix clocks as one device Add PLL driver Fixed a few issues found by Sashiko: register lock, some missing devm_, error handling v2: Fix build issues introduced by checkpatch.pl fixes that I didn't spot earlier. --- Stefan Dösinger (12): dt-bindings: clk: zte: Add zx297520v3 top clock and reset bindings dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset bindings dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset bindings clk: zte: Add Clock registration infrastructure. clk: zte: Add zx PLL support infrastructure clk: zte: Add regmap based clocks clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 LSP clocks reset: zte: Add a zx297520v3 reset driver ARM: dts: zte: Declare zx297520v3 clock device nodes ARM: dts: zte: Add a syscon-reboot for zx297520v3 boards .../bindings/clock/zte,zx297520v3-lspclk.yaml | 130 ++++ .../bindings/clock/zte,zx297520v3-matrixclk.yaml | 180 +++++ .../bindings/clock/zte,zx297520v3-topclk.yaml | 70 ++ MAINTAINERS | 4 + arch/arm/boot/dts/zte/zx297520v3.dtsi | 97 ++- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/zte/Kconfig | 28 + drivers/clk/zte/Makefile | 6 + drivers/clk/zte/clk-regmap.c | 247 +++++++ drivers/clk/zte/clk-zx.c | 157 ++++ drivers/clk/zte/clk-zx.h | 79 ++ drivers/clk/zte/clk-zx297520v3.c | 795 +++++++++++++++++++++ drivers/clk/zte/pll-zx.c | 477 +++++++++++++ drivers/reset/Kconfig | 11 + drivers/reset/Makefile | 1 + drivers/reset/reset-zte-zx297520v3.c | 224 ++++++ include/dt-bindings/clock/zte,zx297520v3-clk.h | 219 ++++++ 18 files changed, 2718 insertions(+), 9 deletions(-) --- base-commit: c1ecb239fa3456529a32255359fc78b69eb9d847 change-id: 20260510-zx29clk-2e4d39e3128c Best regards, -- Stefan Dösinger