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Tue, 16 Jun 2026 13:27:30 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Tue, 16 Jun 2026 23:26:30 +0300 Subject: [PATCH RFC v4 10/12] reset: zte: Add a zx297520v3 reset driver Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260616-zx29clk-v4-10-ca994bd22e9d@gmail.com> References: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com> In-Reply-To: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=11093; i=stefandoesinger@gmail.com; h=from:subject:message-id; bh=/Onf7SXVmixZtmZBhrlI1d4heQCOgMKCksLiEvEpIR4=; b=owEBiQJ2/ZANAwAIAT0TvMhUTxoiAcsmYgBqMbGGZTOmPtLBlyNbaMcWpanSPy4o/C2VjTjma bqpPM5kLaaJAk8EAAEIADkWIQRDFvS2qgVbJ5UyXWw9E7zIVE8aIgUCajGxhhsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDIACgkQPRO8yFRPGiJaUQ//Zc26M1HzXnLUzAvLgAPfOnYSemnKyuN uFndLu41BWHi4OSmYe2We8unIgoWPnA2+QfeVBSX419pVImDFPR40a67Pf+xxfSSiIUXMMEeQIc n7pO3Dn1lE7yXHyeWyb7Xe765VhZCHOPsZ/a2YDGqU/QhRtb++ZVvJWeyUZLPF6/fvOVSgkUWhY UNBjTUzcgh27yJIP54k+D2yY/AKbXgI5xIQpGKCDegm8WT68W+dtuyNwb9WwoeF5aMq5zsvH1UI Y4aSG7+zMzHHuDJRDsPV6mr4Ma9aLf3QVTsktT3o+wC0mcZZWGIjfu2gaTLwti2fPnFST91lwKO hkW+pYbPQCcgq7Rgyit4EQOKR+IRagTxBQBdHg/VyOT3xsRqi4EuuD0G+vqIMjCv7k4npNmMPGL c0KUw4NNMGfx8JGAf89JQ3D5k5AzUkRCNW/kUG0tJ56ac0fLfYi5VMmlH0FW8R1AKc1gI0zgjFO 68d5b/rbAAFAHumx2gc5Og5WwvhAf/O66ebHt7oQlgXOkzRDTVby7bTkbbMMyzyKbtg+5ObXAUV t1wOXMCCjKlRJBeRWrk9fGtMOTXWIqTgY9bQgxhaiQrtIULuqlVCGLHK8nx5IZu6QvRvtmtgf6I Fo+88mc4F62KqSGGlUsUU3NSobc+Aba7etHHmhWueiL5coVe4BTM= X-Developer-Key: i=stefandoesinger@gmail.com; a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This drives the auxiliary devices created by the clock driver. Signed-off-by: Stefan Dösinger --- MAINTAINERS | 1 + drivers/reset/Kconfig | 11 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-zte-zx297520v3.c | 224 +++++++++++++++++++++++++++++++++++ 4 files changed, 237 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f1f0459b2c72..55bf0290343a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3871,6 +3871,7 @@ F: Documentation/devicetree/zte,zx297520v3-* F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ F: drivers/clk/zte/ +F: drivers/reset/reset-zte-zx297520v3.c F: include/dt-bindings/clock/zte,zx297520v3-clk.h ARM/ZYNQ ARCHITECTURE diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d009eb0849a3..116dd23f1b8e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -404,6 +404,17 @@ config RESET_UNIPHIER_GLUE on UniPhier SoCs. Say Y if you want to control reset signals provided by the glue layer. +config RESET_ZTE_ZX297520V3 + tristate "ZTE zx297520v3 Reset Driver" + depends on (ARCH_ZTE || COMPILE_TEST) + default CLK_ZTE_ZX297520V3 + select AUXILIARY_BUS + help + This enables the reset controller for ZTE zx297520v3 SoCs. The reset + controller is part of the clock controller on this SoC. This driver + operates on an auxiliary device exposed by the clock driver. Enable + this driver if you plan to boot the kernel on a zx297520v3 based SoC. + config RESET_ZYNQ bool "ZYNQ Reset Driver" if COMPILE_TEST default ARCH_ZYNQ diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e52569bd276..9a8a48d44dc4 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -50,5 +50,6 @@ obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o obj-$(CONFIG_RESET_TN48M_CPLD) += reset-tn48m.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o +obj-$(CONFIG_RESET_ZTE_ZX297520V3) += reset-zte-zx297520v3.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o diff --git a/drivers/reset/reset-zte-zx297520v3.c b/drivers/reset/reset-zte-zx297520v3.c new file mode 100644 index 000000000000..2022f4df2ebd --- /dev/null +++ b/drivers/reset/reset-zte-zx297520v3.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Stefan Dösinger + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct zte_reset_reg { + u32 mask, wait_mask; + u16 reg; +}; + +struct zte_reset_info { + const struct zte_reset_reg *resets; + unsigned int num; +}; + +struct zte_reset { + struct reset_controller_dev rcdev; + struct regmap *map; + const struct zte_reset_reg *resets; +}; + +static inline struct zte_reset *to_zte_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct zte_reset, rcdev); +} + +static int zx29_rst_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct zte_reset *rst = to_zte_reset(rcdev); + + return regmap_clear_bits(rst->map, rst->resets[id].reg, rst->resets[id].mask); +} + +static int zx29_rst_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct zte_reset *rst = to_zte_reset(rcdev); + int res; + u32 val; + + res = regmap_set_bits(rst->map, rst->resets[id].reg, rst->resets[id].mask); + if (res) + return res; + + /* This is a special case used only by USB reset */ + if (rst->resets[id].wait_mask) { + return regmap_read_poll_timeout(rst->map, rst->resets[id].reg + 4, val, + val & rst->resets[id].wait_mask, 1, 100); + } + + return 0; +} + +static int zx29_rst_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct zte_reset *rst = to_zte_reset(rcdev); + int res; + + res = regmap_test_bits(rst->map, rst->resets[id].reg, rst->resets[id].mask); + if (res < 0) + return res; + + return !res; +} + +static const struct reset_control_ops zx29_rst_ops = { + .assert = zx29_rst_assert, + .deassert = zx29_rst_deassert, + .status = zx29_rst_status, +}; + +static const struct zte_reset_reg zx297520v3_top_resets[] = { + /* This bit is set by ZTE's cpko.ko blob, it looks like a reset bit for the LTE DSP + * coprocessor. Clocks for it are in matrixclk. + */ + [ZX297520V3_ZSP_RESET] = { .reg = 0x13c, .mask = BIT(0) }, + + [ZX297520V3_UART0_RESET] = { .reg = 0x78, .mask = BIT(6) | BIT(7) }, + [ZX297520V3_I2C0_RESET] = { .reg = 0x74, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_RTC_RESET] = { .reg = 0x74, .mask = BIT(4) | BIT(5) }, + [ZX297520V3_TIMER_T08_RESET] = { .reg = 0x78, .mask = BIT(4) | BIT(5) }, + [ZX297520V3_TIMER_T09_RESET] = { .reg = 0x78, .mask = BIT(2) | BIT(3) }, + [ZX297520V3_PMM_RESET] = { .reg = 0x74, .mask = BIT(0) | BIT(1) }, + + /* I haven't found any clocks for GPIO. It probably wouldn't make much + * sense anyway. Only one reset bit per controller. + */ + [ZX297520V3_GPIO_RESET] = { .reg = 0x74, .mask = BIT(3) }, + [ZX297520V3_GPIO8_RESET] = { .reg = 0x74, .mask = BIT(2) }, + + [ZX297520V3_TIMER_T12_RESET] = { .reg = 0x74, .mask = BIT(6) | BIT(7) }, + [ZX297520V3_TIMER_T13_RESET] = { .reg = 0x7c, .mask = BIT(0) | BIT(1) }, + [ZX297520V3_TIMER_T14_RESET] = { .reg = 0x7c, .mask = BIT(2) | BIT(3) }, + [ZX297520V3_TIMER_T15_RESET] = { .reg = 0x74, .mask = BIT(10) | BIT(11) }, + [ZX297520V3_TIMER_T16_RESET] = { .reg = 0x7c, .mask = BIT(4) | BIT(5) }, + [ZX297520V3_TIMER_T17_RESET] = { .reg = 0x12c, .mask = BIT(0) | BIT(1) }, + [ZX297520V3_WDT_T18_RESET] = { .reg = 0x74, .mask = BIT(12) | BIT(13) }, + [ZX297520V3_USIM1_RESET] = { .reg = 0x74, .mask = BIT(14) | BIT(15) }, + [ZX297520V3_AHB_RESET] = { .reg = 0x70, .mask = BIT(0) | BIT(1) }, + + /* USB reset. This is slightly special because it needs to wait for a ready bit after + * deasserting. + */ + [ZX297520V3_USB_RESET] = { .reg = 0x80, .mask = BIT(3) | BIT(4) | BIT(5), + .wait_mask = BIT(1)}, + [ZX297520V3_HSIC_RESET] = { .reg = 0x80, .mask = BIT(0) | BIT(1) | BIT(2), + .wait_mask = BIT(0)}, +}; + +static const struct zte_reset_info zx297520v3_top_info = { + .resets = zx297520v3_top_resets, + .num = ARRAY_SIZE(zx297520v3_top_resets), +}; + +static const struct zte_reset_reg zx297520v3_matrix_resets[] = { + [ZX297520V3_CPU_RESET] = { .reg = 0x28, .mask = BIT(1) }, + [ZX297520V3_EDCP_RESET] = { .reg = 0x68, .mask = BIT(0) }, + [ZX297520V3_SD0_RESET] = { .reg = 0x58, .mask = BIT(1) }, + [ZX297520V3_SD1_RESET] = { .reg = 0x58, .mask = BIT(0) }, + [ZX297520V3_NAND_RESET] = { .reg = 0x58, .mask = BIT(4) }, + [ZX297520V3_PDCFG_RESET] = { .reg = 0x94, .mask = BIT(20) }, + [ZX297520V3_SSC_RESET] = { .reg = 0x94, .mask = BIT(24) }, + [ZX297520V3_GMAC_RESET] = { .reg = 0x114, .mask = BIT(0) | BIT(1) }, + [ZX297520V3_VOU_RESET] = { .reg = 0x16c, .mask = BIT(0) }, +}; + +static const struct zte_reset_info zx297520v3_matrix_info = { + .resets = zx297520v3_matrix_resets, + .num = ARRAY_SIZE(zx297520v3_matrix_resets), +}; + +static const struct zte_reset_reg zx297520v3_lsp_resets[] = { + [ZX297520V3_TIMER_L1_RESET] = { .reg = 0x04, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_WDT_L2_RESET] = { .reg = 0x08, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_WDT_L3_RESET] = { .reg = 0x0c, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_PWM_RESET] = { .reg = 0x10, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_I2S0_RESET] = { .reg = 0x14, .mask = BIT(8) | BIT(9) }, + /* 0x18: Not writeable */ + [ZX297520V3_I2S1_RESET] = { .reg = 0x1c, .mask = BIT(8) | BIT(9) }, + /* 0x20: Not writeable */ + [ZX297520V3_QSPI_RESET] = { .reg = 0x24, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_UART1_RESET] = { .reg = 0x28, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_I2C1_RESET] = { .reg = 0x2c, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_SPI0_RESET] = { .reg = 0x30, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_TIMER_LB_RESET] = { .reg = 0x34, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_TIMER_LC_RESET] = { .reg = 0x38, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_UART2_RESET] = { .reg = 0x3c, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_WDT_LE_RESET] = { .reg = 0x40, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_TIMER_LF_RESET] = { .reg = 0x44, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_SPI1_RESET] = { .reg = 0x48, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_TIMER_L11_RESET] = { .reg = 0x4c, .mask = BIT(8) | BIT(9) }, + [ZX297520V3_TDM_RESET] = { .reg = 0x50, .mask = BIT(8) | BIT(9) }, +}; + +static const struct zte_reset_info zx297520v3_lsp_info = { + .resets = zx297520v3_lsp_resets, + .num = ARRAY_SIZE(zx297520v3_lsp_resets), +}; + +static int reset_zx297520v3_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + const struct zte_reset_info *drv_info; + struct device *dev = &adev->dev; + struct zte_reset *rst; + + drv_info = (struct zte_reset_info *)id->driver_data; + + rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rst->resets = drv_info->resets; + rst->rcdev.owner = THIS_MODULE; + rst->rcdev.nr_resets = drv_info->num; + rst->rcdev.ops = &zx29_rst_ops; + rst->rcdev.of_node = dev->of_node; + rst->rcdev.dev = dev; + rst->rcdev.of_reset_n_cells = 1; + + rst->map = device_node_to_regmap(dev->of_node); + if (IS_ERR(rst->map)) + return dev_err_probe(dev, PTR_ERR(rst->map), "Cannot get parent syscon regmap\n"); + + return devm_reset_controller_register(dev, &rst->rcdev); +} + +static const struct auxiliary_device_id reset_zx297520v3_ids[] = { + { + .name = "clk_zte.zx297520v3_toprst", + .driver_data = (kernel_ulong_t)&zx297520v3_top_info, + }, + { + .name = "clk_zte.zx297520v3_matrixrst", + .driver_data = (kernel_ulong_t)&zx297520v3_matrix_info, + }, + { + .name = "clk_zte.zx297520v3_lsprst", + .driver_data = (kernel_ulong_t)&zx297520v3_lsp_info, + }, + { }, +}; + +MODULE_DEVICE_TABLE(auxiliary, reset_zx297520v3_ids); + +static struct auxiliary_driver reset_zx297520v3_drv = { + .name = "zx297520v3_reset", + .id_table = reset_zx297520v3_ids, + .probe = reset_zx297520v3_probe, +}; + +module_auxiliary_driver(reset_zx297520v3_drv); + +MODULE_AUTHOR("Stefan Dösinger "); +MODULE_DESCRIPTION("ZTE zx297520v3 reset driver"); +MODULE_LICENSE("GPL"); -- 2.53.0