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Tue, 16 Jun 2026 13:27:02 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Tue, 16 Jun 2026 23:26:23 +0300 Subject: [PATCH RFC v4 03/12] dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset bindings Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260616-zx29clk-v4-3-ca994bd22e9d@gmail.com> References: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com> In-Reply-To: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9172; i=stefandoesinger@gmail.com; h=from:subject:message-id; bh=uRtL3tXTNxFSsXIeunxk1WnL31X8l1JDXBwiyONwhLk=; b=owEBiQJ2/ZANAwAIAT0TvMhUTxoiAcsmYgBqMbGGnvcq6tfQFw4fbpiGVAhHG8grApZMUdDUI rdKTTUDY4SJAk8EAAEIADkWIQRDFvS2qgVbJ5UyXWw9E7zIVE8aIgUCajGxhhsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDIACgkQPRO8yFRPGiLy7w//Vn8KOlR9kFU4wiu7vQgPoLA+Jj3qoY4 reoGxqevBcOKtJql+ac2AaQNrfLncREb7f7rnAVegOpGWpPMxvcQaY5mVjSqAUlCW8wuuSa9ev3 3qMRCu2eD2UX1zY46nbjLz04qC3mzSmF16yS9NNDBavCZLNUdjDlwpo8bByLihq/C4h9Kjz2eYc MG0wNJs+P2pyevflaKATcGtqOA8omDd3K6UkDvTerSisOSPLoNwogBT5qYn7nOIE2ErOuHxCY+6 OMDyIn8yEVY2jjI0bq3RwhjoLKWlH/tWczF4RueWV4YQFl6TXptPKaDDA+nqEtIXuiB+VJI1ChT T4+AurmnAe7WiaWUpDUCGIsFdDDrZjU35G6NZazAPnZkHxNY7YYQHCAOJe525sGQ54ecbZTjsom K0Jxr3QneEnDe+U7000SR7YOVazl6LM3NAxBj072N7+JT1XzXR/rkeqV06yNcAyZQBD+mCk0JHm ompM/+C6mHQ6ao6Mv4KAhtgByy7WaFA2fEYvpdsQ+37mPttUMxjmA6qka8FwmApZyKvZwHgg9kQ GIkI6LZZGoO/Vg6HMxOZMeinL3B9Hi1H/1uFeFUzNGmiCyS8xPeNly3LqEc53an+FCm2IdRm7X4 9RQirwQhe6s/zq3y/lLE4rC1PGoRLhW1mr8OosRjDbJnMcCXBVdI= X-Developer-Key: i=stefandoesinger@gmail.com; a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 The clock controller of the Low Speed Peripherals is relatively clean. One register per device with gates, muxes and resets and for some devices a divider. There are even bits in the top controller to control propagation of clock lines down to LSP. The clocks are sorted by register address and I am convinced that the device list is complete. There are however a few more registers that are likely helper controls for the I2S and TDM devices. Signed-off-by: Stefan Dösinger --- Patch changelog: v5: Order properties compatible->reg->clocks->clock->names->#cells --- .../bindings/clock/zte,zx297520v3-lspclk.yaml | 130 +++++++++++++++++++++ include/dt-bindings/clock/zte,zx297520v3-clk.h | 56 +++++++++ 2 files changed, 186 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspclk.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspclk.yaml new file mode 100644 index 000000000000..096295edb6e2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspclk.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/zte,zx297520v3-lspclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx297520v3 SoC LSP clock and reset controller + +maintainers: + - Stefan Dösinger + +description: | + This clock and reset controller controls low speed peripherals on the board. + This is a relatively isolated subsystem containing UART, I2C, I2S and SPI + devices. The clock controller is responsible for bringing the devices out of + reset and enabling their clocks as needed. + + The controller receives its clock signal from the matrix controller and need + to be declared as clock inputs. + + All available clocks are defined as preprocessor macros in the + 'dt-bindings/clock/zte,zx297520v3-clk.h' header. + +properties: + compatible: + const: zte,zx297520v3-lspclk + + reg: + maxItems: 1 + + clocks: + items: + - description: Main PLL divided by 5 output from matrixclk (124.8 MHz) + - description: Main PLL divided by 4 output from matrixclk (156 MHz) + - description: Main PLL divided by 6 output from matrixclk (104 MHz) + - description: Main PLL divided by 8 output from matrixclk (78 MHz) + - description: Main PLL divided by 12 output from matrixclk (52 MHz) + - description: Main oscillator output from matrixclk (26 MHz) + - description: Timer oscillator output from matrixclk (32 KHz) + - description: LSP pclk output from matrixclk (26 MHz) + - description: TDM wclk mux output from matrixclk + - description: DPLL divided by 4 output from matrixclk (122.88 MHz) + + clock-names: + items: + - const: mpll_d5 + - const: mpll_d4 + - const: mpll_d6 + - const: mpll_d8 + - const: mpll_d12 + - const: osc26m + - const: osc32k + - const: pclk + - const: tdm_wclk + - const: dpll_d4 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + matrixclk: clock-controller@1306000 { + compatible = "zte,zx297520v3-matrixclk", "syscon"; + reg = <0x01306000 0x400>; + clocks = <&osc26m>, <&osc32k>, + <&topclk ZX297520V3_MPLL>, <&topclk ZX297520V3_MPLL_D2>, + <&topclk ZX297520V3_MPLL_D3>, <&topclk ZX297520V3_MPLL_D4>, + <&topclk ZX297520V3_MPLL_D5>, <&topclk ZX297520V3_MPLL_D6>, + <&topclk ZX297520V3_MPLL_D8>, <&topclk ZX297520V3_MPLL_D12>, + <&topclk ZX297520V3_MPLL_D16>, <&topclk ZX297520V3_MPLL_D26>, + <&topclk ZX297520V3_UPLL>, <&topclk ZX297520V3_UPLL_D2>, + <&topclk ZX297520V3_UPLL_D3>, <&topclk ZX297520V3_UPLL_D4>, + <&topclk ZX297520V3_UPLL_D5>, <&topclk ZX297520V3_UPLL_D6>, + <&topclk ZX297520V3_UPLL_D8>, <&topclk ZX297520V3_UPLL_D12>, + <&topclk ZX297520V3_UPLL_D16>, + <&topclk ZX297520V3_DPLL>, <&topclk ZX297520V3_DPLL_D2>, + <&topclk ZX297520V3_DPLL_D3>, <&topclk ZX297520V3_DPLL_D4>, + <&topclk ZX297520V3_DPLL_D5>, <&topclk ZX297520V3_DPLL_D6>, + <&topclk ZX297520V3_DPLL_D8>, <&topclk ZX297520V3_DPLL_D12>, + <&topclk ZX297520V3_DPLL_D16>, + <&topclk ZX297520V3_GPLL>, <&topclk ZX297520V3_GPLL_D2>, + <&topclk ZX297520V3_GPLL_D3>, <&topclk ZX297520V3_GPLL_D4>, + <&topclk ZX297520V3_GPLL_D5>, <&topclk ZX297520V3_GPLL_D6>, + <&topclk ZX297520V3_GPLL_D8>, <&topclk ZX297520V3_GPLL_D12>, + <&topclk ZX297520V3_GPLL_D16>; + clock-names = "osc26m", "osc32k", "mpll", "mpll_d2", "mpll_d3", + "mpll_d4", "mpll_d5", "mpll_d6", "mpll_d8", "mpll_d12", + "mpll_d16", "mpll_d26", "upll", "upll_d2", "upll_d3", + "upll_d4", "upll_d5", "upll_d6", "upll_d8", "upll_d12", + "upll_d16", "dpll", "dpll_d2", "dpll_d3", "dpll_d4", + "dpll_d5", "dpll_d6", "dpll_d8", "dpll_d12", "dpll_d16", + "gpll", "gpll_d2", "gpll_d3", "gpll_d4", "gpll_d5", + "gpll_d6", "gpll_d8", "gpll_d12", "gpll_d16"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock-controller@1400000 { + compatible = "zte,zx297520v3-lspclk"; + reg = <0x01400000 0x100>; + clocks = <&matrixclk ZX297520V3_LSP_MPLL_D5_WCLK>, + <&matrixclk ZX297520V3_LSP_MPLL_D4_WCLK>, + <&matrixclk ZX297520V3_LSP_MPLL_D6_WCLK>, + <&matrixclk ZX297520V3_LSP_MPLL_D8_WCLK>, + <&matrixclk ZX297520V3_LSP_MPLL_D12_WCLK>, + <&matrixclk ZX297520V3_LSP_OSC26M_WCLK>, + <&matrixclk ZX297520V3_LSP_OSC32K_WCLK>, + <&matrixclk ZX297520V3_LSP_PCLK>, + <&matrixclk ZX297520V3_LSP_TDM_WCLK>, + <&matrixclk ZX297520V3_LSP_DPLL_D4_WCLK>; + clock-names = "mpll_d5", "mpll_d4", "mpll_d6", "mpll_d8", "mpll_d12", + "osc26m", "osc32k", "pclk", "tdm_wclk", "dpll_d4"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h index 815e8ceeb64e..57387529a708 100644 --- a/include/dt-bindings/clock/zte,zx297520v3-clk.h +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h @@ -160,4 +160,60 @@ #define ZX297520V3_GMAC_RESET 7 #define ZX297520V3_VOU_RESET 8 +#define ZX297520V3_TIMER_L1_WCLK 1 +#define ZX297520V3_TIMER_L1_PCLK 2 +#define ZX297520V3_WDT_L2_WCLK 3 +#define ZX297520V3_WDT_L2_PCLK 4 +#define ZX297520V3_WDT_L3_WCLK 5 +#define ZX297520V3_WDT_L3_PCLK 6 +#define ZX297520V3_PWM_WCLK 7 +#define ZX297520V3_PWM_PCLK 8 +#define ZX297520V3_I2S0_WCLK 9 +#define ZX297520V3_I2S0_PCLK 10 +#define ZX297520V3_I2S1_WCLK 11 +#define ZX297520V3_I2S1_PCLK 12 +#define ZX297520V3_QSPI_WCLK 13 +#define ZX297520V3_QSPI_PCLK 14 +#define ZX297520V3_UART1_WCLK 15 +#define ZX297520V3_UART1_PCLK 16 +#define ZX297520V3_I2C1_WCLK 17 +#define ZX297520V3_I2C1_PCLK 18 +#define ZX297520V3_SPI0_WCLK 19 +#define ZX297520V3_SPI0_PCLK 20 +#define ZX297520V3_TIMER_LB_WCLK 21 +#define ZX297520V3_TIMER_LB_PCLK 22 +#define ZX297520V3_TIMER_LC_WCLK 23 +#define ZX297520V3_TIMER_LC_PCLK 24 +#define ZX297520V3_UART2_WCLK 25 +#define ZX297520V3_UART2_PCLK 26 +#define ZX297520V3_WDT_LE_WCLK 27 +#define ZX297520V3_WDT_LE_PCLK 28 +#define ZX297520V3_TIMER_LF_WCLK 29 +#define ZX297520V3_TIMER_LF_PCLK 30 +#define ZX297520V3_SPI1_WCLK 31 +#define ZX297520V3_SPI1_PCLK 32 +#define ZX297520V3_TIMER_L11_WCLK 33 +#define ZX297520V3_TIMER_L11_PCLK 34 +#define ZX297520V3_TDM_WCLK 35 +#define ZX297520V3_TDM_PCLK 36 + +#define ZX297520V3_TIMER_L1_RESET 0 +#define ZX297520V3_WDT_L2_RESET 1 +#define ZX297520V3_WDT_L3_RESET 2 +#define ZX297520V3_PWM_RESET 3 +#define ZX297520V3_I2S0_RESET 4 +#define ZX297520V3_I2S1_RESET 5 +#define ZX297520V3_QSPI_RESET 6 +#define ZX297520V3_UART1_RESET 7 +#define ZX297520V3_I2C1_RESET 8 +#define ZX297520V3_SPI0_RESET 9 +#define ZX297520V3_TIMER_LB_RESET 10 +#define ZX297520V3_TIMER_LC_RESET 11 +#define ZX297520V3_UART2_RESET 12 +#define ZX297520V3_WDT_LE_RESET 13 +#define ZX297520V3_TIMER_LF_RESET 14 +#define ZX297520V3_SPI1_RESET 15 +#define ZX297520V3_TIMER_L11_RESET 16 +#define ZX297520V3_TDM_RESET 17 + #endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */ -- 2.53.0