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Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260616-zx29clk-v4-4-ca994bd22e9d@gmail.com> References: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com> In-Reply-To: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=11496; i=stefandoesinger@gmail.com; h=from:subject:message-id; bh=qum6l8+tCrrqR02yHwh3t4yH0w6TRVXfiZs3oZFSBbY=; b=owEBiQJ2/ZANAwAIAT0TvMhUTxoiAcsmYgBqMbGGvZqzCIpbWjYc5d7M1aNl2DjTTdzYR2Kq2 ig8adoeMGKJAk8EAAEIADkWIQRDFvS2qgVbJ5UyXWw9E7zIVE8aIgUCajGxhhsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDIACgkQPRO8yFRPGiKEKBAAoyvFxBhwoWKuc9d5nb7HQWGArjoDaAy 98GoacliWT6n/v5nS8F9r5cRNcr9UL/inhK80tv3dMtprYK4SWA9QHbIPlbGOWx9riFjf157yYj hnK5ynhEbEO3KmzasZAboD92Ee3cgljkUNXGw/Am9C9Ray7lO3GunuFgyGuE3bf2l8efMkJQz04 1dj0yJ0c6PzM8+7kFLS+SDrKUfGcR+fwFg2ej1eni8vUCBfdEYLLyCVKpiiqN1e2FeOzPhIUnIy T2Sr5ro82ik4vmkiaQM9F+iVdaiBQAi2V+5ouCL0DK/9oiMkWT0RZjl7LiFfv/IYZBaJMomjJ/2 OUQ+pSsl9n3O9PYcSVmCFaiN6T5ddKAcgT3tw6/r7dMZjrCe83zZzjVYaxg1p5JhwLuBSuhEowr XdtZfykGXdKmPICd7mSUXS1eK1Mr2zvqHyWZXfRqzgBmxru0YCuF3gNB+JbYckTjVt5yqQBRXB1 9HMRge3gJ82G2Qqn5D1lJLqxvMUHpC8B7MizSeTU4FRj5Os4nTlZ/BJ6+4d1vP7BEP5hIoBIM5z au+2P4sBmZCoPaR+2WbKtRleLuiZ8hNk4hwAbYGdSqb/cSY2xtvf/XziAlAxqmCS8wufNexys4w bomTXjdrfQhL+1lwANc3j/hUGSP1+3JpQMz2bWeOzsIGtM/I1QvU= X-Developer-Key: i=stefandoesinger@gmail.com; a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 The next patches will implement the regmap clocks and PLL driver. The actual hardware specific clock listing will live in a separate module. Signed-off-by: Stefan Dösinger --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/zte/Kconfig | 17 +++++ drivers/clk/zte/Makefile | 5 ++ drivers/clk/zte/clk-regmap.c | 30 +++++++++ drivers/clk/zte/clk-zx.c | 157 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/zte/clk-zx.h | 79 ++++++++++++++++++++++ drivers/clk/zte/pll-zx.c | 19 ++++++ 9 files changed, 310 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0cc1ede3c80c..f1f0459b2c72 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3870,6 +3870,7 @@ F: Documentation/devicetree/bindings/arm/zte.yaml F: Documentation/devicetree/zte,zx297520v3-* F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ +F: drivers/clk/zte/ F: include/dt-bindings/clock/zte,zx297520v3-clk.h ARM/ZYNQ ARCHITECTURE diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1717ce75a907..6f0a863951ca 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -545,6 +545,7 @@ source "drivers/clk/uniphier/Kconfig" source "drivers/clk/visconti/Kconfig" source "drivers/clk/x86/Kconfig" source "drivers/clk/xilinx/Kconfig" +source "drivers/clk/zte/Kconfig" source "drivers/clk/zynqmp/Kconfig" # Kunit test cases diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index cc108a75a900..13a5478f1112 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -167,5 +167,6 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_X86) += x86/ endif obj-y += xilinx/ +obj-$(CONFIG_COMMON_CLK_ZTE) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/ diff --git a/drivers/clk/zte/Kconfig b/drivers/clk/zte/Kconfig new file mode 100644 index 000000000000..b7b65a2172a9 --- /dev/null +++ b/drivers/clk/zte/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# ZTE Clock Drivers +# + +config COMMON_CLK_ZTE + tristate "Clock driver for ZTE SoCs" + depends on ARCH_ZTE || COMPILE_TEST + default ARCH_ZTE + select AUXILIARY_BUS + select MFD_SYSCON + help + This option selects common clock infrastructure for ZTE based SoCs. + You will need to enable one or more SoC specific drivers to make use + of this. + + Enable this if you are building a kernel for a ZTE designed board. diff --git a/drivers/clk/zte/Makefile b/drivers/clk/zte/Makefile new file mode 100644 index 000000000000..27db07293165 --- /dev/null +++ b/drivers/clk/zte/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_COMMON_CLK_ZTE) += clk-zte.o + +clk-zte-y += clk-zx.o pll-zx.o clk-regmap.o diff --git a/drivers/clk/zte/clk-regmap.c b/drivers/clk/zte/clk-regmap.c new file mode 100644 index 000000000000..7908f1562f63 --- /dev/null +++ b/drivers/clk/zte/clk-regmap.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (c) 2018 BayLibre, SAS. + * Copyright (c) 2026 Stefan Dösinger. + * Author: Stefan Dösinger + */ + +#include "clk-zx.h" + +int zx_clk_register_gates(struct device *dev, struct regmap *regmap, + const struct zx_gate_desc *desc, unsigned int num, + struct clk_hw_onecell_data *clocks) +{ + return -ENODEV; +} + +int zx_clk_register_dividers(struct device *dev, struct regmap *regmap, + const struct zx_div_desc *desc, unsigned int num, + struct clk_hw_onecell_data *clocks) +{ + return -ENODEV; +} + +int zx_clk_register_muxes(struct device *dev, struct regmap *regmap, + const struct zx_mux_desc *desc, unsigned int num, + struct clk_hw_onecell_data *clocks) +{ + return -ENODEV; +} diff --git a/drivers/clk/zte/clk-zx.c b/drivers/clk/zte/clk-zx.c new file mode 100644 index 000000000000..6e21c4a82a46 --- /dev/null +++ b/drivers/clk/zte/clk-zx.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Stefan Dösinger + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk-zx.h" + +static void zx_adev_release(struct device *dev) +{ + dev_info(dev, "Aux device released.\n"); +} + +static void zx_adev_unregister(void *data) +{ + struct auxiliary_device *adev = data; + + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +int zx_clk_probe(struct platform_device *pdev) +{ + unsigned int public_clk_count = 1, highest_id = 0; + struct clk_hw_onecell_data *clocks; + struct device *dev = &pdev->dev; + const struct zx_clk_data *data; + struct auxiliary_device *adev; + struct regmap *map; + struct clk *clk; + unsigned int i; + int res; + + data = device_get_match_data(dev); + if (!data) + return -EINVAL; + + map = device_node_to_regmap(dev->of_node); + if (!map) + return -EINVAL; + + for (i = 0; i < data->num_plls; ++i) { + if (data->plls[i].id) { + unsigned int last_idx = data->plls[i].id + data->plls[i].num_postdivs - 1; + + if (last_idx > highest_id) + highest_id = last_idx; + public_clk_count += data->plls[i].num_postdivs; + } + } + for (i = 0; i < data->num_muxes; ++i) { + if (data->muxes[i].id) { + if (data->muxes[i].id > highest_id) + highest_id = data->muxes[i].id; + public_clk_count++; + } + } + for (i = 0; i < data->num_divs; ++i) { + if (data->divs[i].id) { + if (data->divs[i].id > highest_id) + highest_id = data->divs[i].id; + public_clk_count++; + } + } + for (i = 0; i < data->num_gates; ++i) { + if (data->gates[i].id) { + if (data->gates[i].id > highest_id) + highest_id = data->gates[i].id; + public_clk_count++; + } + } + + if (WARN_ON(public_clk_count != highest_id + 1)) + return -EINVAL; + + clocks = devm_kzalloc(dev, struct_size(clocks, hws, public_clk_count), GFP_KERNEL); + if (!clocks) + return -ENOMEM; + clocks->num = public_clk_count; + + for (i = 0; i < data->num_inputs_enable; ++i) { + clk = devm_clk_get_enabled(dev, data->inputs_enable[i]); + if (IS_ERR(clk)) { + return dev_err_probe(dev, PTR_ERR(clk), "Input clk %s failure\n", + data->inputs_enable[i]); + } + } + for (i = 0; i < data->num_inputs; ++i) { + clk = devm_clk_get(dev, data->inputs[i]); + if (IS_ERR(clk)) { + return dev_err_probe(dev, PTR_ERR(clk), "Input clk %s failure\n", + data->inputs[i]); + } + } + + res = zx_clk_register_plls(dev, map, data->plls, data->num_plls, clocks); + if (res) + return res; + + res = zx_clk_register_muxes(dev, map, data->muxes, data->num_muxes, clocks); + if (res) + return res; + + res = zx_clk_register_dividers(dev, map, data->divs, data->num_divs, clocks); + if (res) + return res; + + res = zx_clk_register_gates(dev, map, data->gates, data->num_gates, clocks); + if (res) + return res; + + /* This is to catch holes in the tables rather than registration errors. The count vs + * highest ID should catch most static issues. This check here will trigger if an ID is + * reused by accident. + */ + for (i = 1; i < public_clk_count; i++) { + if (WARN(!clocks->hws[i], "Clock %u not registered\n", i)) + return -EINVAL; + } + + res = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clocks); + if (res) + return res; + + adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL); + if (!adev) + return -ENOMEM; + + adev->name = data->reset_auxdev_name; + adev->dev.parent = dev; + adev->dev.release = zx_adev_release; + adev->dev.of_node = dev->of_node; + + res = auxiliary_device_init(adev); + if (res) + return dev_err_probe(dev, res, "Failed to init aux dev %s\n", adev->name); + + res = auxiliary_device_add(adev); + if (res) { + auxiliary_device_uninit(adev); + return dev_err_probe(dev, res, "Failed to add aux dev %s\n", adev->name); + } + + return devm_add_action_or_reset(dev, zx_adev_unregister, adev); +} +EXPORT_SYMBOL_NS_GPL(zx_clk_probe, "ZTE_CLK"); + +MODULE_AUTHOR("Stefan Dösinger "); +MODULE_DESCRIPTION("ZTE common clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/zte/clk-zx.h b/drivers/clk/zte/clk-zx.h new file mode 100644 index 000000000000..b39bbed2d420 --- /dev/null +++ b/drivers/clk/zte/clk-zx.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Stefan Dösinger + */ + +#ifndef __DRV_CLK_ZX_H +#define __DRV_CLK_ZX_H + +#include +#include +#include + +struct zx_pll_desc { + unsigned int id; + const char *name; + const char * const *parents; + unsigned int num_parents; + unsigned long rate; + const unsigned int *postdivs; + unsigned int num_postdivs; + u16 reg; +}; + +struct zx_mux_desc { + unsigned int id; + const char *name; + const char * const *parents; + unsigned int num_parents; + u16 reg; + u8 shift, size; +}; + +struct zx_div_desc { + unsigned int id; + const char *name, *parent; + u16 reg; + u8 shift, size; +}; + +struct zx_gate_desc { + unsigned int id; + const char *name, *parent; + unsigned long flags; + u16 reg; + u8 shift; +}; + +int zx_clk_register_plls(struct device *dev, struct regmap *regmap, + const struct zx_pll_desc *desc, unsigned int num, + struct clk_hw_onecell_data *clocks); +int zx_clk_register_muxes(struct device *dev, struct regmap *regmap, + const struct zx_mux_desc *desc, unsigned int num, + struct clk_hw_onecell_data *clocks); +int zx_clk_register_dividers(struct device *dev, struct regmap *regmap, + const struct zx_div_desc *desc, unsigned int num, + struct clk_hw_onecell_data *clocks); +int zx_clk_register_gates(struct device *dev, struct regmap *regmap, + const struct zx_gate_desc *desc, unsigned int num, + struct clk_hw_onecell_data *clocks); + +struct zx_clk_data { + const char * const *inputs_enable; + unsigned int num_inputs_enable; + const char * const *inputs; + unsigned int num_inputs; + const struct zx_pll_desc *plls; + unsigned int num_plls; + const struct zx_mux_desc *muxes; + unsigned int num_muxes; + const struct zx_div_desc *divs; + unsigned int num_divs; + const struct zx_gate_desc *gates; + unsigned int num_gates; + const char *reset_auxdev_name; +}; + +int zx_clk_probe(struct platform_device *pdev); + +#endif /* __DRV_CLK_ZX_H */ diff --git a/drivers/clk/zte/pll-zx.c b/drivers/clk/zte/pll-zx.c new file mode 100644 index 000000000000..c0475d5441fb --- /dev/null +++ b/drivers/clk/zte/pll-zx.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Stefan Dösinger + */ +#include +#include +#include +#include +#include +#include + +#include "clk-zx.h" + +int zx_clk_register_plls(struct device *dev, struct regmap *regmap, + const struct zx_pll_desc *desc, unsigned int num, + struct clk_hw_onecell_data *clocks) +{ + return -ENODEV; +} -- 2.53.0