Re: [PATCH v3 2/3] perf: marvell: Add CN20K LLC-TAD PMU support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch series reverses the registration order of the PMU and CPU hotplug, creating a race window where the PMU is exposed to userspace before hotplug migration is wired up.
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commit 71b7ba2b271b1080739c44e37ec7465ecb45ee0e
Author: Geetha sowjanya <gakula@marvell.com>

perf: marvell: Add CN20K LLC-TAD PMU support

Add support for the LLC Tag-and-Data (TAD) PMU present in
Marvell CN20K SoCs.

> diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn10k_tad_pmu.c
> index 69a6648fa6648..cd81bf8ff5690 100644
> --- a/drivers/perf/marvell_cn10k_tad_pmu.c
> +++ b/drivers/perf/marvell_cn10k_tad_pmu.c

[ ... ]

> @@ -478,7 +521,7 @@ static int tad_pmu_probe(struct platform_device *pdev)
>  		.read		= tad_pmu_event_counter_read,
>  	};
>  
> -	if (version == TAD_PMU_V1) {
> +	if (version == TAD_PMU_V1 || version == TAD_PMU_V3) {
>  		tad_pmu->pmu.attr_groups = tad_pmu_attr_groups;
>  		tad_pmu->ops		 = &tad_pmu_ops;
>  	} else {

[Severity: Medium]
Looking at the remainder of tad_pmu_probe(), the registration order is:

	ret = perf_pmu_register(&tad_pmu->pmu, "tad", -1);
	if (ret) {
		dev_err(&pdev->dev, "Error %d registering perf PMU\n", ret);
		return ret;
	}

	ret = cpuhp_state_add_instance_nocalls(tad_pmu_cpuhp_state,
					       &tad_pmu->node);

Does this sequence create a race window where the PMU is exposed to
userspace before hotplug migration is wired up?

If userspace immediately creates events assigned to tad_pmu->cpu, and that
CPU goes offline before the hotplug state instance is added, the hotplug
callback wouldn't be invoked to migrate the context. This could leave the
PMU tied to an offline CPU, preventing its events from being scheduled.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260616071149.12523-1-gakula@marvell.com?part=2