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Wed, 17 Jun 2026 04:08:11 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434ac9cf01sm15873609b3a.11.2026.06.17.04.08.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jun 2026 04:08:10 -0700 (PDT) From: Taniya Das Date: Wed, 17 Jun 2026 16:37:53 +0530 Subject: [PATCH v2 2/4] dt-bindings: clock: qcom: Add EVA clock and reset controller for Glymur SoC Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com> References: <20260617-evacc_glymur-v2-0-905108dacaaa@oss.qualcomm.com> In-Reply-To: <20260617-evacc_glymur-v2-0-905108dacaaa@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: dSoHEMPf51onN1-iI_hRMCPruD6NqxEL X-Authority-Analysis: v=2.4 cv=IeC3n2qa c=1 sm=1 tr=0 ts=6a32801c cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=QUVFY6MdtzYYwQCb-hMA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDEwNSBTYWx0ZWRfX0oogCauwK+r7 ljgzwj8TTYmGTb7hvMJVZAkqi2bMqxvKFUlk6WNO0Y2/4K/ulvOahtW/84R/UXy3tJ19fecIs/u wiObBLAgpfTEAnqxO6RX1bMLUM6gHQQ= X-Proofpoint-ORIG-GUID: dSoHEMPf51onN1-iI_hRMCPruD6NqxEL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDEwNSBTYWx0ZWRfXysEK3hl0d+Ci /Ph5OZKKVMtOJhlkx+eP5atG6tCN2WW+13D1ui0modOjgmAQa258MaImVW7HkkLQ2CEKKJ/z80q KfvFoM2QVYx5f0rjOccUdZ4xGQsTMmce1BBFv2HFkbIgXBV97JvDkGc/0aSVRiLF6p4DJZ0DsHX bc9YsQ7WI2io0ofB8OePhmHhKWO9sC7nxZmzfDqkX72b4/mS5bDBUacGJh6UIcpN7U82Ca07WHV /qqz9k3T/tTIeg0oCXYiKEm6hH6KTTFNETF4dYJKUwT8WeaBXiPvpr1WOo24UvSzM3hHT1zSLbu ItlFwjWBkDDD7V6KszMbylnvSQzck+HuiJrIsQ5HxejECSzz2qDrCi55sD+nV2mHUflpRkQzyc5 3Ojfg/rpMANLF+iPtz0vzYQbSyWdwv5+iZladD3760/ykCn7/0Fh0T8nvQ4k81EUKIMl8x79BBH W54XT9ZvUNHpQBDL6Mg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_01,2026-06-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606170105 Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Reviewed-by: Rob Herring (Arm) Signed-off-by: Taniya Das --- .../bindings/clock/qcom,glymur-evacc.yaml | 72 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,glymur-evacc.h | 38 ++++++++++++ 2 files changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fb0bc1acc920e906033e04fe38bf500c24247e5a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-evacc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm EVA Clock & Reset Controller on Glymur SoC + +maintainers: + - Taniya Das + +description: | + Qualcomm EVA clock control module which supports the clocks, resets and + power domains for the EVA instances on Glymur SoC. + + See also: + - include/dt-bindings/clock/qcom,glymur-evacc.h + +properties: + compatible: + const: qcom,glymur-evacc + + clocks: + items: + - description: Interface clock from GCC + - description: Board XO source + - description: Sleep clock source + + power-domains: + items: + - description: MMCX power domain + - description: MXC power domain + + required-opps: + description: + Required OPP nodes for the MMCX and MXC power domains. + items: + - description: MMCX performance point + - description: MXC performance point + +required: + - compatible + - clocks + - power-domains + - required-opps + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ab00000 { + compatible = "qcom,glymur-evacc"; + reg = <0x0ab00000 0x10000>; + clocks = <&gcc GCC_EVA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,glymur-evacc.h b/include/dt-bindings/clock/qcom,glymur-evacc.h new file mode 100644 index 0000000000000000000000000000000000000000..35a7b4550351661bdb1f7bdfbeec625fafdfcef7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-evacc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H + +/* EVA_CC clocks */ +#define EVA_CC_AHB_CLK 0 +#define EVA_CC_AHB_CLK_SRC 1 +#define EVA_CC_MVS0_CLK 2 +#define EVA_CC_MVS0_CLK_SRC 3 +#define EVA_CC_MVS0_DIV_CLK_SRC 4 +#define EVA_CC_MVS0_FREERUN_CLK 5 +#define EVA_CC_MVS0_SHIFT_CLK 6 +#define EVA_CC_MVS0C_CLK 7 +#define EVA_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define EVA_CC_MVS0C_FREERUN_CLK 9 +#define EVA_CC_MVS0C_SHIFT_CLK 10 +#define EVA_CC_PLL0 11 +#define EVA_CC_SLEEP_CLK 12 +#define EVA_CC_SLEEP_CLK_SRC 13 +#define EVA_CC_XO_CLK 14 +#define EVA_CC_XO_CLK_SRC 15 + +/* EVA_CC power domains */ +#define EVA_CC_MVS0_GDSC 0 +#define EVA_CC_MVS0C_GDSC 1 + +/* EVA_CC resets */ +#define EVA_CC_INTERFACE_BCR 0 +#define EVA_CC_MVS0_BCR 1 +#define EVA_CC_MVS0C_CLK_ARES 2 +#define EVA_CC_MVS0C_BCR 3 +#define EVA_CC_MVS0C_FREERUN_CLK_ARES 4 + +#endif /* _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H */ -- 2.34.1