From: sashiko-bot@kernel.org
To: "Jad Keskes" <inasj268@gmail.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 1/2] dt-bindings: rng: timeriomem_rng: add width and mask properties
Date: Wed, 17 Jun 2026 11:37:01 +0000 [thread overview]
Message-ID: <20260617113701.8831B1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260617112642.1897096-1-inasj268@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Use of non-standard `width` property instead of `reg-io-width`.
--
commit 7dac0db93dcf3017652753bebd5c0a2a7a2a06b5
Author: Jad Keskes <inasj268@gmail.com>
dt-bindings: rng: timeriomem_rng: add width and mask properties
Add optional width (8, 16, 32) and mask properties to the binding. The width
selects the bus access size for reads, while the mask allows filtering out
non-entropy-bearing bits.
> diff --git a/Documentation/devicetree/bindings/rng/timeriomem_rng.yaml b/Documentation/devicetree/bindings/rng/timeriomem_rng.yaml
> index 4754174e9849b..636305f211c88 100644
> --- a/Documentation/devicetree/bindings/rng/timeriomem_rng.yaml
> +++ b/Documentation/devicetree/bindings/rng/timeriomem_rng.yaml
[ ... ]
> @@ -26,16 +40,26 @@ properties:
> instead. Note that the default quality is usually zero which disables
> using this rng to automatically fill the kernel's entropy pool.
>
> - reg:
> - maxItems: 1
> + width:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 32
> + enum: [8, 16, 32]
> description:
> - Base address to sample from. Currently 'reg' must be at least four bytes
> - wide and 32-bit aligned.
> + Access width in bits. Determines whether the read is performed as
> + an 8-bit, 16-bit, or 32-bit bus access.
[Severity: Low]
Should this binding use the standard reg-io-width property (representing the
width in bytes) instead of introducing a custom width property in bits?
Using the established reg-io-width standard prevents fragmentation of the
device tree API conventions for specifying memory-mapped I/O access width.
> +
> + mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0xFFFFFFFF
> + description:
> + Mask applied to the value read from the register. Bits set to 0 in
> + the mask are cleared in the output data. Default (no mask) passes
> + all bits through.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260617112642.1897096-1-inasj268@gmail.com?part=1
prev parent reply other threads:[~2026-06-17 11:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-17 11:26 [PATCH v3 1/2] dt-bindings: rng: timeriomem_rng: add width and mask properties Jad Keskes
2026-06-17 11:26 ` [PATCH v3 2/2] hw_random: timeriomem-rng: add configurable read width and data mask Jad Keskes
2026-06-17 11:41 ` sashiko-bot
2026-06-17 11:37 ` sashiko-bot [this message]
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