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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1781820289; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fmxnn1xGV2jaajdnAkd2F39mWtMrhqNNBNCjdjH9eY0=; b=x+Uen+Nt1+OxcZfqH03ULWKV0ZCy18GV0zzXWj8kubsqFXhoFiEWFQKNqjD1jlVoBSM7+J 94HnrgKSp5WS/3P8wcV67OyPVeuWeo6Sdsnw5APviHfubLjOMmp590WaTiLnxz6TTHuiEw 91RtYhKCpN/doc5tUCNtpfOurW9hAR53bRfMySj3S5yynUl65mcDUEUMpI1pCPLY+qNuex hIeQ5SUvch9RYS+PW5BIOAWBLTn6thNKT0BXz/mSw74ckyqedc0rjQSfiY/roJFJyjJqol MPUBqQVodHLfw1J1G/DPAaBNE+uax3sYuvgMJnh7RcONttooNSgVKK5+PZadWg== To: linux-pci@vger.kernel.org Cc: Marek Vasut , Marc Zyngier , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Catalin Marinas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 2/4] irqchip/gic-v3: Refactor GIC600 limited to 32bit PA erratum handling Date: Fri, 19 Jun 2026 00:02:00 +0200 Message-ID: <20260618220427.14325-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260618220427.14325-1-marek.vasut+renesas@mailbox.org> References: <20260618220427.14325-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-MBO-RS-META: 7x7fbqfctmuyj5g17moafybc439uyhxs X-MBO-RS-ID: 7e6c2e40ea8eb87b0b8 X-Rspamd-Queue-Id: 4ghFBq09hGz9vCL The GIC600 implementation is now known to be used on multiple 64-bit SoCs, where it has address width for AXI or APB interface configured to 32 bit, and it can access only the first 4GiB of physical address space. Rework the handling of the quirk to work around this limitation such that new entries can be added purely as new compatible strings, with no need to add additional functions or new its_quirk array entries. Suggested-by: Marc Zyngier Signed-off-by: Marek Vasut --- V2: New patch --- Cc: "Krzysztof Wilczyński" Cc: Bjorn Helgaas Cc: Catalin Marinas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Marc Zyngier Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- drivers/irqchip/irq-gic-v3-its.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index b57d81ad33a0a..8ec2175b78288 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -4890,10 +4890,17 @@ static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data) return true; } -static bool __maybe_unused its_enable_rk3568002(void *data) +static const char * const dma_32bit_impaired_platforms[] = { +#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 + "rockchip,rk3566", + "rockchip,rk3568", +#endif + NULL, +}; + +static bool __maybe_unused its_enable_dma32(void *data) { - if (!of_machine_is_compatible("rockchip,rk3566") && - !of_machine_is_compatible("rockchip,rk3568")) + if (!of_machine_compatible_match(dma_32bit_impaired_platforms)) return false; gfp_flags_quirk |= GFP_DMA32; @@ -4968,14 +4975,12 @@ static const struct gic_quirk its_quirks[] = { .property = "dma-noncoherent", .init = its_set_non_coherent, }, -#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 { - .desc = "ITS: Rockchip erratum RK3568002", + .desc = "ITS: Broken GIC600 integration limited to 32bit PA", .iidr = 0x0201743b, .mask = 0xffffffff, - .init = its_enable_rk3568002, + .init = its_enable_dma32, }, -#endif { } }; -- 2.53.0