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Fri, 19 Jun 2026 00:04:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1781820300; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/gMsmz/YVE+vex624i9NCwCdWl2Dy91mu9dYa478yfA=; b=YEu1MySBlTTkRPRDUXRH4jfDLqNMW5trPKTlqI8QJNIVNRw6eTVAoFVTMw8LpDX5CoblDM CnYnniCS2LtA0Omfrc1Ch3a6SJssfcbVHPrCbejPgtOdDgmRajaI1fzf6NF6TAd+6OVWHA a4FzZdSCR9uOZg2kl0cKuyHeGk9ShQu4CZ+XYcJuYXrQF8uNAeawPmclkrtyHpEQYwwpa6 yYZ3ofvSa7NCnUhKKxX2DFfLhfA5wFwm2t1XKPcJC16u0PzFQ8hH144njBj1JQLsa2+vIk xasJQCchsKZkNfZzC5W4rBrlkHgnQbEBgcSr2oS7uc77/XRkCsMvRT5713e/LA== Authentication-Results: outgoing_mbo_mout; dkim=pass header.d=mailbox.org header.s=mail20150812 header.b=iJkRsskG; spf=pass (outgoing_mbo_mout: domain of marek.vasut+renesas@mailbox.org designates 2001:67c:2050:b231:465::102 as permitted sender) smtp.mailfrom=marek.vasut+renesas@mailbox.org From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1781820297; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/gMsmz/YVE+vex624i9NCwCdWl2Dy91mu9dYa478yfA=; b=iJkRsskGUq9n3yhN9deqfE9wDG1YvTU0vlkBfAiZxC5Y7G1SE/rVSLHwIdaKEvJAA4LhoT 8ZHx48YBeL8VdAshTOvVPzwqm1m+Gr9Udb28DFTJGovhzNAcRY4FgPkzhb9Xczmmg9UQBX inKdSssn8rO73e8YP619obT6OZV3+AzlB1b7F96Ax5OE6mLfCdEg+YckqQtxoVc2fDww6Z TSrFpX+WL8fQX7I/KZAHtE/7Tp5tclHZK2/3qt1uWCZC0MV3pZiXS2wzPJZuGw6AzpLQST cJmgL7tFizqYHgNhLrKE4CMgOc6mr1Pn49+qlPRFhUjrsYcZz6gNxTE43x7t3A== To: linux-pci@vger.kernel.org Cc: Marek Vasut , Yoshihiro Shimoda , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Catalin Marinas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Marc Zyngier , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 4/4] arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes Date: Fri, 19 Jun 2026 00:02:02 +0200 Message-ID: <20260618220427.14325-5-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260618220427.14325-1-marek.vasut+renesas@mailbox.org> References: <20260618220427.14325-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-MBO-RS-ID: 091e0d6cf64cfdacc1c X-MBO-RS-META: br8xtrt6op6jwhtum4eaywqiog95jbzs X-Rspamd-Queue-Id: 4ghFBz6X9Nz9tsX This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this SoC can use it. Add GIC ITS node into GIC node, update interrupt-map and add msi-map into PCIe controller node. The GIC ITS does have master interface to issue transactions to RAM. The interface does support cacheable transactions, however, it does not support shareable attribute, because the AXI port signals are tied to inactive in this implementation. Therefore, add "dma-noncoherent" DT property into the GIC ITS subnode. The GIC redistributor does not have cacheable/shareable, therefore add "dma-noncoherent" DT property into the GIC node. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Marek Vasut --- NOTE: This would not be possible without prior work from Shimoda-san https://lore.kernel.org/all/20240214052144.1966569-1-yoshihiro.shimoda.uh@renesas.com/ --- Cc: "Krzysztof Wilczyński" Cc: Bjorn Helgaas Cc: Catalin Marinas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Marc Zyngier Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 31 ++++++++++++++++------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 3a8af825bb253..82e864acf2601 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -792,6 +792,7 @@ pciec0: pcie@e65d0000 { resets = <&cpg 624>; reset-names = "pwr"; max-link-speed = <4>; + msi-parent = <&its>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; @@ -802,10 +803,10 @@ pciec0: pcie@e65d0000 { dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; @@ -839,6 +840,7 @@ pciec1: pcie@e65d8000 { resets = <&cpg 625>; reset-names = "pwr"; max-link-speed = <4>; + msi-parent = <&its>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; @@ -849,10 +851,10 @@ pciec1: pcie@e65d8000 { dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; @@ -2131,11 +2133,22 @@ ipmmu_mm: iommu@eefc0000 { gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; - #address-cells = <0>; + #address-cells = <2>; + #size-cells = <2>; interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = ; + dma-noncoherent; + + ranges = <0x0 0x0 0x0 0xf1000000 0x0 0x200000>; + + its: msi-controller@40000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x40000 0x0 0x20000>; + dma-noncoherent; + msi-controller; + }; }; gpu: gpu@fd000000 { -- 2.53.0