From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org,
guodong@riscstar.com, dfustini@oss.tenstorrent.com,
michal.simek@amd.com, junhui.liu@pigmoral.tech,
darshan.prajapati@einfochips.com, akpm@linux-foundation.org,
zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com,
pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com,
jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com,
robin.randhawa@sifive.com, scott@riscstar.com,
dave.patel@riscstar.com, raymond.mao@riscstar.com,
Yu-Chien Peter Lin <peter.lin@sifive.com>
Subject: [RFC PATCH 1/3] dt-bindings: riscv: Add Worlds ISA extensions
Date: Fri, 19 Jun 2026 18:58:32 +0800 [thread overview]
Message-ID: <20260619105834.1277302-2-peter.lin@sifive.com> (raw)
In-Reply-To: <20260619105834.1277302-1-peter.lin@sifive.com>
Add DT bindings for RISC-V Worlds ISA extensions to tag
transactions with World IDs that hardware uses to enforce
world-based isolation across execution contexts.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 2b0a8a93bb21..1bc8b1aa67c0 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -193,12 +193,35 @@ properties:
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
+ - const: smlwid
+ description: |
+ The standard Smlwid extension for M-mode control of lower
+ privilege World ID via the mlwid CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
+ - const: smlwidlist
+ description: |
+ The standard Smlwidlist extension for M-mode control of lower
+ privilege World IDs via the mlwidlist CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
- const: smstateen
description: |
The standard Smstateen extension for controlling access to CSRs
added by other RISC-V extensions in H/S/VS/U/VU modes and as
ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+ - const: smwdeleg
+ description: |
+ The standard Smwdeleg extension for M-mode delegation of lower
+ privilege World ID control to S-mode via the mwiddeleg CSR, as
+ ratified at commit TBD ("TBD") of riscv-worlds.
+
+ - const: smwid
+ description: |
+ The standard Smwid extension for M-mode World ID control via the
+ mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds.
+
- const: ssaia
description: |
The standard Ssaia supervisor-level extension for the advanced
@@ -262,6 +285,12 @@ properties:
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
+ - const: sswid
+ description: |
+ The standard Sswid extension for S-mode control of lower
+ privilege World IDs via the slwid CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
- const: supm
description: |
The standard Supm extension for pointer masking support in user
--
2.43.7
next prev parent reply other threads:[~2026-06-19 10:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-19 10:58 [RFC PATCH 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-06-19 10:58 ` Yu-Chien Peter Lin [this message]
2026-06-19 10:57 ` [RFC PATCH 1/3] dt-bindings: riscv: Add Worlds ISA extensions sashiko-bot
2026-06-19 10:58 ` [RFC PATCH 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-06-19 10:59 ` sashiko-bot
2026-06-19 10:58 ` [RFC PATCH 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-06-19 10:59 ` sashiko-bot
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