From: sashiko-bot@kernel.org
To: "Qiang Yu" <qiang.yu@oss.qualcomm.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v6 6/8] arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR
Date: Mon, 22 Jun 2026 05:21:15 +0000 [thread overview]
Message-ID: <20260622052115.6188C1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260621-tcsr_qref_0622-v6-6-c939c22ded0c@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing regulator definitions for Mahua USB and EDP clock references, leading to unpowered PHY components.
--
commit e43024044dc26df2e1498b871bce2a3a9aa15cab
Author: Qiang Yu <qiang.yu@oss.qualcomm.com>
arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR
The TCSR clkref_en clocks gate the QREF block which provides reference
clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF
and refgen blocks on the CRD board.
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index c98dfb3941fa3..92b929ee3448c 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
[ ... ]
> @@ -278,6 +278,26 @@ &smb2370_k_e2_eusb2_repeater {
> vdd3-supply = <&vreg_l7b_e0_2p79>;
> };
>
> +&tcsr {
> + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>;
> + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>;
> + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>;
> + vdda-qrefrpt3-0p9-supply = <&vreg_l2h_e0_0p72>;
> + vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>;
> + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>;
> + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>;
> + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>;
> + vdda-qrefrx4-0p9-supply = <&vreg_l2h_e0_0p72>;
> + vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0_0p72>;
> + vdda-qreftx0-0p9-supply = <&vreg_l3f_e0_0p72>;
> + vdda-qreftx0-1p2-supply = <&vreg_l4h_e0_1p2>;
> + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>;
> + vdda-refgen3-0p9-supply = <&vreg_l2f_e0_0p82>;
> + vdda-refgen3-1p2-supply = <&vreg_l4h_e0_1p2>;
> + vdda-refgen4-0p9-supply = <&vreg_l1f_e1_0p82>;
> + vdda-refgen4-1p2-supply = <&vreg_l4f_e1_1p08>;
> +};
[Severity: High]
Does this setup overlook the regulator definitions for Mahua USB and EDP clock
references?
In drivers/clk/qcom/tcsrcc-glymur.c, the tcsr_cc_mahua_clk_descs array omits
.regulator_names and .num_regulators for all USB and EDP clocks:
drivers/clk/qcom/tcsrcc-glymur.c:tcsr_cc_mahua_clk_descs[] = {
[TCSR_EDP_CLKREF_EN] = {
.name = "tcsr_edp_clkref_en",
.offset = 0x60,
},
...
The qcom,mahua-tcsr DT binding and the Mahua CRD explicitly list and require
regulators for these blocks: vdda-qrefrpt3-0p9-supply,
vdda-qrefrpt4-0p9-supply, vdda-qrefrpt5-0p9-supply, and
vdda-qrefrx3-0p9-supply.
Because .num_regulators is 0 for these clocks, qcom_clk_ref_register() will
not call devm_regulator_bulk_get(), and qcom_clk_ref_prepare() will never
enable the regulators.
Can this cause a silent hardware failure where major peripherals like USB and
EDP PHYs are conceptually enabled but their corresponding TCSR QREF blocks
remain completely unpowered?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260621-tcsr_qref_0622-v6-0-c939c22ded0c@oss.qualcomm.com?part=6
next prev parent reply other threads:[~2026-06-22 5:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 5:11 [PATCH v6 0/8] clk: qcom: Add common clkref support and migrate Glymur and Mahua Qiang Yu
2026-06-22 5:11 ` [PATCH v6 1/8] dt-bindings: clock: qcom: Move glymur TCSR to own binding Qiang Yu
2026-06-22 5:18 ` sashiko-bot
2026-06-22 7:30 ` Krzysztof Kozlowski
2026-06-22 7:29 ` Krzysztof Kozlowski
2026-06-22 5:11 ` [PATCH v6 2/8] dt-bindings: clock: qcom,glymur-tcsr: Add mahua support Qiang Yu
2026-06-22 5:16 ` sashiko-bot
2026-06-22 7:32 ` Krzysztof Kozlowski
2026-06-22 9:51 ` Qiang Yu
2026-06-22 5:11 ` [PATCH v6 3/8] clk: qcom: Add generic clkref_en support Qiang Yu
2026-06-22 5:24 ` sashiko-bot
2026-06-22 5:11 ` [PATCH v6 4/8] clk: qcom: tcsrcc-glymur: Add regulator supplies and migrate to clk_ref helper Qiang Yu
2026-06-22 5:11 ` [PATCH v6 5/8] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support Qiang Yu
2026-06-22 5:21 ` sashiko-bot
2026-06-22 5:11 ` [PATCH v6 6/8] arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR Qiang Yu
2026-06-22 5:21 ` sashiko-bot [this message]
2026-06-22 5:11 ` [PATCH v6 7/8] arm64: dts: qcom: mahua: " Qiang Yu
2026-06-22 5:22 ` sashiko-bot
2026-06-22 5:11 ` [PATCH v6 8/8] arm64: dts: qcom: mahua: Switch pcie5_phy ref clock to RPMH_CXO_CLK Qiang Yu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260622052115.6188C1F00A3A@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=qiang.yu@oss.qualcomm.com \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox