From: Ashish Mhetre <amhetre@nvidia.com>
To: <joro@8bytes.org>, <will@kernel.org>, <robin.murphy@arm.com>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<jonathanh@nvidia.com>, <thierry.reding@kernel.org>,
<nicolinc@nvidia.com>
Cc: <iommu@lists.linux.dev>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Ashish Mhetre <amhetre@nvidia.com>
Subject: [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example
Date: Mon, 22 Jun 2026 06:54:09 +0000 [thread overview]
Message-ID: <20260622065410.2780215-1-amhetre@nvidia.com> (raw)
The CMDQV interrupt on Tegra264 is edge-triggered per the hardware
interrupt documentation, but the binding example describes it as
level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so
that it does not propagate the wrong trigger type.
Fixes: 8a59954192eb ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support")
Reported-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
---
.../devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
index 3f5006a59805..76ef34fe5c72 100644
--- a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
+++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
@@ -38,5 +38,5 @@ examples:
cmdqv@5200000 {
compatible = "nvidia,tegra264-cmdqv";
reg = <0x5200000 0x830000>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
};
--
2.50.1
next reply other threads:[~2026-06-22 6:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 6:54 Ashish Mhetre [this message]
2026-06-22 6:54 ` [PATCH 2/2] arm64: tegra: Fix CMDQV interrupt type on Tegra264 Ashish Mhetre
2026-06-22 16:38 ` [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example Conor Dooley
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