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Tue, 23 Jun 2026 23:13:37 -0700 (PDT) Received: from inhnjlux1020.ls.ege.ds ([103.28.245.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c74469913esm124643625ad.82.2026.06.23.23.13.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2026 23:13:36 -0700 (PDT) From: Udaya Kiran Challa To: tsbogend@alpha.franken.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, me@brighamcampbell.com, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Udaya Kiran Challa Subject: [PATCH] spi: dt-bindings: microchip,pic32mzda-sqi: Convert to DT schema Date: Wed, 24 Jun 2026 11:43:29 +0530 Message-Id: <20260624061329.130468-1-challauday369@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert Microchip PIC32 Quad SPI controller devicetree binding from legacy text format to DT schema. Signed-off-by: Udaya Kiran Challa --- .../bindings/spi/microchip,pic32mzda-sqi.yaml | 53 +++++++++++++++++++ .../devicetree/bindings/spi/sqi-pic32.txt | 18 ------- 2 files changed, 53 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml delete mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt diff --git a/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml b/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml new file mode 100644 index 000000000000..39f06b61e894 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/microchip,pic32mzda-sqi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32MZDA Quad SPI controller + +maintainers: + - Thomas Bogendoerfer + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: microchip,pic32mzda-sqi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: spi_ck + - const: reg_ck + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + sqi1: spi@1f8e2000 { + compatible = "microchip,pic32mzda-sqi"; + reg = <0x1f8e2000 0x200>; + interrupts = <169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>; + clock-names = "spi_ck", "reg_ck"; + }; diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt b/Documentation/devicetree/bindings/spi/sqi-pic32.txt deleted file mode 100644 index c82d021bce50..000000000000 --- a/Documentation/devicetree/bindings/spi/sqi-pic32.txt +++ /dev/null @@ -1,18 +0,0 @@ -Microchip PIC32 Quad SPI controller ------------------------------------ -Required properties: -- compatible: Should be "microchip,pic32mzda-sqi". -- reg: Address and length of SQI controller register space. -- interrupts: Should contain SQI interrupt. -- clocks: Should contain phandle of two clocks in sequence, one that drives - clock on SPI bus and other that drives SQI controller. -- clock-names: Should be "spi_ck" and "reg_ck" in order. - -Example: - sqi1: spi@1f8e2000 { - compatible = "microchip,pic32mzda-sqi"; - reg = <0x1f8e2000 0x200>; - clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>; - clock-names = "spi_ck", "reg_ck"; - interrupts = <169 IRQ_TYPE_LEVEL_HIGH>; - }; -- 2.34.1